公开(公告)号：US5600600A

公开(公告)日：1997-02-04

申请号：US381530

申请日：1995-01-31

Applicant: Marco Olivo ,  Marco Maccarrone

Inventor： Marco Olivo ,  Marco Maccarrone

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C7/00

CPC classification number: G11C29/46 ,  G11C29/14

Abstract: A method for testing an electrically programmable non-volatile memory including a cell matrix and an internal state machine which governs the succession and timing of the memory programming phases includes excluding the internal state machine, modifying at least one of the control signals to program the cell matrix, and verifying programming correctness.

Abstract translation: 一种用于测试包括单元矩阵的电可编程非易失性存储器和控制存储器编程阶段的连续和定时的内部状态机的方法包括：排除内部状态机，修改至少一个控制信号以编程单元 矩阵和验证编程正确性。

公开(公告)号：US5592633A

公开(公告)日：1997-01-07

申请号：US223949

申请日：1994-04-06

Applicant: Marco Casis ,  Giorgio Pedrazzini

Inventor： Marco Casis ,  Giorgio Pedrazzini

IPC: H04L29/06 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4068

Abstract: While employing the same number of dedicated pins of an IC, a self-configurable interface circuit between a control bus and the IC recognizes whether the IC is being used in a system employing an SPI or a I2CBUS protocol for the transmission to the IC of control signals through the bus. The interface circuit employs an "inner" SPI interface standard block, to a third input of which either a true CE (chip-enable) signal coming from a third wire of the bus or a virtual CE signal that is self-generated by the interface circuit in case of operation in an I2CBUS environment, is fed. The third (ADDR) pin of the IC may be connected to the CE wire of the bus in case of an SPI application or it may be biased at the supply or ground voltage for selecting one or the other of two internal addresses of the IC, when functioning in an I2CBUS environment.

Abstract translation: 在采用相同数量的IC专用引脚的情况下，控制总线和IC之间的自配置接口电路可以识别是否在使用SPI或I2CBUS协议的系统中使用IC来传输到控制IC 通过公交车信号。 接口电路使用“内部”SPI接口标准块，到第三个输入，其中来自总线第三条线路的真正CE（芯片使能）信号或由接口自发生成的虚拟CE信号 在I2CBUS环境中运行的情况下，电路被馈送。 在SPI应用的情况下，IC的第三个（ADDR）引脚可以连接到总线的CE引线，或者可能被偏置在电源或地电压上，用于选择IC的两个内部地址中的一个或另一个， 当在I2CBUS环境中工作时。

公开(公告)号：US5592418A

公开(公告)日：1997-01-07

申请号：US367068

申请日：1995-01-03

Applicant: Marco Sabatini ,  Alan Kramer

Inventor： Marco Sabatini ,  Alan Kramer

IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: H01L29/7881 ,  H01L29/1033

Abstract: Non-volatile memory cell with double level of polycrystalline silicon has a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

Abstract translation: 具有双层多晶硅的非易失性存储单元具有源极区（38），漏极区（31），所述源极和漏极区之间的沟道区（34），浮置栅极（33）和控制栅极 （32），其中沟道区域区域延伸到两个栅极下方并垂直于源极 - 漏极方向的两个侧向区域中。

公开(公告)号：US5587946A

公开(公告)日：1996-12-24

申请号：US212907

申请日：1994-03-15

Applicant: Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

Inventor： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/02

CPC classification number: G11C16/04 ,  G11C16/0416 ,  G11C16/30

Abstract: To reduce read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. The threshold voltage of nonselected cells (i.e., the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to a "body effect", whereby the threshold voltage depends on the voltage drop between the source terminal and the substrate. The source line of a selected cell is biased to a positive value greater than that of the bit line of the selected cell. Methods for reading, writing and erasing cells using certain voltage levels are disclosed.

Abstract translation: 为了减少由于耗尽的存储器阵列单元即使未被选择而导通的读取和写入错误，非选择的存储器单元被偏置以使浮动端子和端子相对于衬底区域处于正电压。 非选择单元的阈值电压（即，用于导通的单元的栅极和源极端子之间的最小电压）由于“体效应”而增加，由此阈值电压取决于源极端子与源极端子之间的电压降 基质。 所选单元格的源极线被偏置为大于所选单元的位线的正值。 公开了使用特定电压电平读取，写入和擦除单元的方法。

公开(公告)号：US5583820A

公开(公告)日：1996-12-10

申请号：US366211

申请日：1994-12-29

Applicant: Silvia Padoan ,  Marco Olivo ,  Carla Golla

Inventor： Silvia Padoan ,  Marco Olivo ,  Carla Golla

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/407

CPC classification number: G11C5/143 ,  G11C16/30 ,  G11C5/147

Abstract: A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

Abstract translation: 一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。 比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。 稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。 电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。

公开(公告)号：US5581509A

公开(公告)日：1996-12-03

申请号：US356740

申请日：1994-12-15

Applicant: Carla M. Golla ,  Marco Olivo

Inventor： Carla M. Golla ,  Marco Olivo

IPC: G11C17/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/76 ,  G11C16/08 ,  G11C29/82 ,  G11C8/12

Abstract: A double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy comprises a plurality of identical circuit blocks supplied with address signals and each one generating a respective selection signal which is activated by a particular logic configuration of said address signals for the selection of a particular row of the matrix; each one of said circuit blocks also generates a carry-out signal which is supplied to a carry-in input of a following circuit block and is activated when the respective selection signal is activated; a first circuit block of said plurality of circuit blocks has the respective carry-in input connected to a reference voltage; each of said circuit blocks is also supplied with a control signal, which is activated by a control circuitry of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row is addressed, to enable the activation of the respective selection signal if the carry-out signal supplying the respective carry-in input is activated, so that two adjacent rows can be simultaneously selected.

Abstract translation: 用于具有冗余的电可擦除和可编程非易失性存储器件的双行地址解码和选择电路包括提供有地址信号的多个相同的电路块，并且每个电路块产生相应的选择信号，该选择信号由特定逻辑配置 所述地址信号用于选择矩阵的特定行; 所述电路块中的每一个还产生提供给后续电路块的进位输入的进位信号，并且当各个选择信号被激活时被激活; 所述多个电路块的第一电路块具有连接到参考电压的相应输入输入; 每个所述电路块还被提供有控制信号，该控制信号由存储器件的控制电路激活，当在存储器件的电擦除之前的预编程操作期间寻址有缺陷的行时，以使得能够激活 如果提供相应进位输入的进位信号被激活，则相应的选择信号被激活，使得可以同时选择两个相邻的行。

公开(公告)号：US5581455A

公开(公告)日：1996-12-03

申请号：US454645

申请日：1995-05-31

Applicant: Domenico Rossi ,  Hisashi Tahara

Inventor： Domenico Rossi ,  Hisashi Tahara

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/78 ,  H01L29/92 ,  H02M3/07 ,  H02M7/00

CPC classification number: H02M3/07

Abstract: A BiCMOS capacitive charge pump circuit for low supply voltage has a bipolar part, functionally reproducing a basic charge pump circuit and a CMOS part that comprises MOS transistors functionally connected in parallel with the driving switch toward ground potential of the charge transfer capacitance and in parallel with the output diode for substantially nullifying voltage drops on the respective bipolar components. A special driving circuit (T8, R2, I2), powered at the boosted output voltage (VOUT) responds to the rise of the voltage on the output node above a minimum level, as ensured by the bipolar part of the charge pump circuit, to drive said MOS transistors (M1, M2), thus allowing the output voltage to reach a level that is substantially double the supply voltage (Vs), even when the latter is exceptionally low, for reliably ensuring switching of the CMOS part of the circuit.

Abstract translation: 用于低电源电压的BiCMOS电容电荷泵电路具有双极性部分，功能地再现基本电荷泵电路和CMOS部件，其包括与驱动开关并联连接的MOS晶体管朝向电荷转移电容的接地电位并与 用于基本无效的输出二极管在相应的双极组件上下降。 在升压输出电压（VOUT）下供电的特殊驱动电路（T8，R2，I2）响应于输出节点上的电压上升到最小电平以上，由电荷泵电路的双极部分确保， 驱动所述MOS晶体管（M1，M2），从而允许输出电压达到基本上是电源电压（Vs）的两倍的水平，即使后者特别低，为了可靠地确保电路的CMOS部分的切换。

公开(公告)号：USRE35379E

公开(公告)日：1996-11-19

申请号：US189576

申请日：1994-01-28

Applicant: Germano Nicollini

Inventor： Germano Nicollini

IPC: H03F3/00 ,  H03H19/00 ,  H03F1/34

CPC classification number: H03F3/005 ,  H03H19/004

Abstract: The filter comprises at least one completely differential operational amplifier having two inputs and two outputs and at least one pair of feedback circuits connecting said outputs with respective inputs of said amplifier outside of same. The operational amplifier has no common-mode feedback circuit, whose functions are performed by said feedback circuits external to the amplifier.

Abstract translation: 滤波器包括至少一个具有两个输入和两个输出的完全差分运算放大器，以及至少一对反馈电路，其将所述输出与所述放大器的相应输入连接在一起。 运算放大器没有共模反馈电路，其功能由放大器外部的所述反馈电路执行。

公开(公告)号：US5576648A

公开(公告)日：1996-11-19

申请号：US202043

申请日：1994-02-23

Applicant: Giorgio Rossi ,  Franco Cocetta ,  Fabio Marchio

Inventor： Giorgio Rossi ,  Franco Cocetta ,  Fabio Marchio

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/58 ,  H03K17/082 ,  H03K17/14 ,  H03K17/16 ,  H03K17/687 ,  H03K3/00 ,  G05F1/40

CPC classification number: H03K17/168 ,  H03K17/0822 ,  H03K17/165

Abstract: A circuit for controlled discharge of energy stored in an inductive load, comprising an active semiconductor device (T) connected serially with the inductive load (L) between first and second terminals of a voltage supply source and having a control terminal for connection to a driver circuit (C), and a control circuit (R1, R2, COMP) connected between the inductive load and said control terminal. The control circuit comprises a voltage divider (R1, R2) connected between the inductive load (L) and the first terminal of the voltage supply source, and a comparator (COMP) having first and second input terminals respectively connected to the voltage divider and to a voltage reference and an output terminal which is coupled to the control terminal of the active element (T).

Abstract translation: 一种用于受控放电存储在电感负载中的能量的电路，包括与电压源的第一和第二端子之间的感性负载（L）串联连接的有源半导体器件（T），并且具有用于连接到驱动器 电路（C）和连接在感性负载和所述控制端子之间的控制电路（R1，R2，COMP）。 控制电路包括连接在感性负载（L）和电压源的第一端之间的分压器（R1，R2）和具有分别连接到分压器的第一和第二输入端的比较器（COMP）和 电压基准和输出端子，其耦合到有源元件（T）的控制端子。

公开(公告)号：US5563816A

公开(公告)日：1996-10-08

申请号：US384211

申请日：1995-02-06

Applicant: Carla Golla ,  Mauro L. Sali

Inventor： Carla Golla ,  Mauro L. Sali

IPC: H03H21/00 ,  H03H17/02 ,  H03H17/06 ,  G06F15/31

CPC classification number: H03H17/0607

Abstract: A high-resolution digital filter including a memory structure receiving as input a sampled digital signal, and an adder chain with delay blocks connected between the adder chain and the memory structure. The adders are connected to memory outputs to convert the input signal into an output signal having predetermined frequency response characteristics. The memory structure includes at least one pair of non-volatile memory elements, each memory element being input one portion only of the sampled signal.

Abstract translation: 包括接收采样数字信号作为输入的存储器结构的高分辨率数字滤波器和连接在加法器链和存储器结构之间的具有延迟块的加法器链。 加法器连接到存储器输出以将输入信号转换成具有预定频率响应特性的输出信号。 存储器结构包括至少一对非易失性存储器元件，每个存储器元件仅输入采样信号的一部分。