公开(公告)号：US12113843B2

公开(公告)日：2024-10-08

申请号：US16912491

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Ozgur Oyman

IPC: H04L65/70 ,  H04L65/1016 ,  H04L65/65 ,  H04L65/80 ,  H04N19/167 ,  H04N19/597

CPC classification number: H04L65/70 ,  H04L65/1016 ,  H04L65/65 ,  H04L65/80 ,  H04N19/167 ,  H04N19/597

Abstract: Embodiments herein provide mechanisms for a receiving device to indicate to a transmitting device viewport information to indicate a region of interest for point cloud video content. For example, the receiving device may transmit a real-time transport control protocol (RTCP) feedback message that includes the viewport information. The viewport information includes an indication of a reference point for the region of interest. The receiving device may receive, from the transmitting device, the point cloud video for the region of interest based on the viewport information. Other embodiments may be described and claimed.

公开(公告)号：US12113026B2

公开(公告)日：2024-10-08

申请号：US18377991

申请日：2023-10-09

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US12111775B2

公开(公告)日：2024-10-08

申请号：US17212722

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Duane E. Galbi ,  Matthew J. Adiletta ,  Hugh Wilkinson ,  Patrick Connor

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F13/1668 ,  G06F13/409 ,  G06F13/4221

Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.

公开(公告)号：US20240333946A1

公开(公告)日：2024-10-03

申请号：US18193806

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Venkateshan Udhayan ,  Kristoffer Fleming ,  Chia-Hung S. Kuo ,  Sangeeta Manepalli ,  Vishal Sinha ,  Jason Tanner

IPC: H04N19/30 ,  H04N19/14 ,  H04N19/164 ,  H04N19/172

CPC classification number: H04N19/30 ,  H04N19/14 ,  H04N19/164 ,  H04N19/172

Abstract: A video source device for wireless display sharing, including: an encoder operable to dynamically switch between encoding a video full-frame into a first bitstream at a first resolution, and a video sub-frame into a second bitstream at a second resolution, wherein the second resolution is higher than the first resolution; processing circuitry operable to decide between encoding the video full-frame and encoding the video sub-frame based on an amount of available wireless transmission bandwidth, a number of pixels in a changed region of the video full-frame, spatial complexity of a changed region of the video full-frame, temporal complexity of a changed region of the video full-frame, or a category of region change of the video full-frame; and a transmitter operable to wirelessly transmit the first bitstream and the second bitstream to a video sink device.

公开(公告)号：US20240333940A1

公开(公告)日：2024-10-03

申请号：US18128747

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Phoenix WORTH ,  Faouzi KOSSENTINI ,  Foued BEN AMARA

IPC: H04N19/146

CPC classification number: H04N19/146

Abstract: A system that includes at least one memory and circuitry coupled to the at least one memory, wherein the circuitry is to access media from the at least one memory, wherein the circuitry is to: select one or more settings to apply to encode the video based on a cost of signaling applicable settings.

公开(公告)号：US20240333904A1

公开(公告)日：2024-10-03

申请号：US18193419

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Niloufar Pourian

IPC: H04N13/264 ,  H04N13/271

CPC classification number: H04N13/264 ,  H04N13/271 ,  H04N2013/0092 ,  H04N2013/0096 ,  H04N2213/007

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to generate optical flow maps based on foreground and background image segmentation are disclosed. Example apparatus disclosed herein are to generate a reference optical flow map based on a stereo pair of background images corresponding to a first camera field-of-view and a second camera field-of-view, and generate a first optical flow map based on a stereo pair of input images corresponding to the first camera field-of-view and the second camera field-of-view. Disclosed example apparatus are also to combine the reference optical flow map and the first optical flow map based on an alpha matte to generate a second optical flow map associated with the stereo pair of input images, the alpha matte representative of segmentation of at least one of the stereo pair of input images into foreground and background regions.

公开(公告)号：US20240333602A1

公开(公告)日：2024-10-03

申请号：US18574793

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Hai Tao WANG ,  Yong LI ,  Kailun QIN ,  Chengye LI

IPC: H04L41/16 ,  G06N3/091 ,  G16Y20/20 ,  G16Y40/35 ,  G16Y40/40

CPC classification number: H04L41/16 ,  G06N3/091 ,  G16Y20/20 ,  G16Y40/35 ,  G16Y40/40

Abstract: Systems, apparatuses and methods include technology that identifies a model update that originates from a plurality of IoT devices. The technology determines votes from the plurality of IoT devices, where the votes indicate whether the model update will be deployed. The technology deploys the model update to the plurality of IoT devices based on the votes.

公开(公告)号：US20240333501A1

公开(公告)日：2024-10-03

申请号：US18194553

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Salmin Sultana ,  Karanvir S. Grewal ,  Sergej Deutsch

IPC: H04L9/14 ,  G06F21/60 ,  G06F21/62 ,  G06F21/78

CPC classification number: H04L9/14 ,  G06F21/602 ,  G06F21/6209 ,  G06F21/6218 ,  G06F21/78

Abstract: In a technique of hardware thread isolation, a processor comprises a first core including a first hardware thread register. The core is to select a first key identifier stored in the first hardware thread register in response to receiving a first memory access request associated with a first hardware thread of a process. Memory controller circuitry coupled to the first core is to obtain a first encryption key associated with the first key identifier. The first key identifier may be selected from the first hardware thread register based, at least in part, on a first portion of a pointer of the first memory access request. The first key identifier selected from the first hardware thread register is to be appended to a physical address translated from a linear address at least partially included in the pointer.

公开(公告)号：US20240333472A1

公开(公告)日：2024-10-03

申请号：US18194270

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu Mathew ,  Avinash V. Varna ,  Kirk S. YAP

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/0637

Abstract: An apparatus of an aspect includes a substitution box (S-box) circuitry. The S-box circuitry includes multiplicative inverse circuitry. The multiplicative inverse circuitry is to receive an 8-bit input in Galois field and is to generate a corresponding 8-bit output in Galois field. The 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. The apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the S-box circuitry to receive the 8-bit output. The error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20240333471A1

公开(公告)日：2024-10-03

申请号：US18190308

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu Mathew ,  Sachin Taneja

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/0637

Abstract: In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.