FinFET device having reduce capacitance, access resistance, and contact resistance
    41.
    发明申请
    FinFET device having reduce capacitance, access resistance, and contact resistance 有权
    FinFET器件具有降低电容,访问电阻和接触电阻

    公开(公告)号:US20120193713A1

    公开(公告)日:2012-08-02

    申请号:US13017966

    申请日:2011-01-31

    IPC分类号: H01L29/772 H01L21/336

    摘要: A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

    摘要翻译: 形成具有减小的电容,存取电阻和接触电阻的鳍状场效应晶体管(finFET)器件。 提供掩埋氧化物,鳍状物,栅极和第一间隔物。 该鳍被掺杂以形成在栅极下方延伸的延伸结。 第二间隔件形成在延伸接头的顶部。 每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。 延伸结和未被栅极保护的埋入氧化物,第一间隔物和第二间隔物被回蚀刻以产生空隙。 空隙填充有半导体材料,使得半导体材料的顶表面延伸到延伸接头的顶表面之下,以形成凹陷的源极 - 漏极区域。 在凹陷的源极 - 漏极区域,延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

    Stressed Fin-FET devices with low contact resistance
    42.
    发明授权
    Stressed Fin-FET devices with low contact resistance 有权
    具有低接触电阻的强调Fin-FET器件

    公开(公告)号:US08207038B2

    公开(公告)日:2012-06-26

    申请号:US12786397

    申请日:2010-05-24

    IPC分类号: H01L21/336

    摘要: A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.

    摘要翻译: 公开了一种用于制造FET器件的方法。 该方法包括具有由第一材料构成的翅片的Fin-FET器件,然后通过外延沉积第二材料而合并在一起。 翅片是使用选择性蚀刻的垂直凹部。 在第一材料和第二材料的增加的表面积上形成连续的硅化物层,导致较小的电阻。 覆盖FET器件的应力衬垫之后被沉积。 还公开了一种FET器件,该FET器件包括多个Fin-FET器件,其翅片由第一材料构成。 FET器件包括第二材料,其外延地融合鳍片。 翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层,以及覆盖该器件的应力衬垫。

    Two-dimensional patterning employing self-assembled material
    43.
    发明授权
    Two-dimensional patterning employing self-assembled material 有权
    采用自组装材料的二维图案

    公开(公告)号:US08207028B2

    公开(公告)日:2012-06-26

    申请号:US12017598

    申请日:2008-01-22

    IPC分类号: H01L21/336 H01L21/8234

    摘要: A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

    摘要翻译: 具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的第一纳米级自对准自组装嵌套线结构由第一层内的第一自组装嵌段共聚物形成。 第一层填充有填充材料,并且第二层沉积在包含第一纳米级嵌套线结构的第一层之上。 具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层内的第二自组装嵌段共聚物形成。 第一纳米级嵌套线结构和第二纳米级嵌套线结构的复合图案被转移到第一层下面的底层中以形成在两个方向上包含周期性的结构阵列。

    STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs
    45.
    发明申请
    STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs 失效
    紧凑型长沟道FET的结构和方法

    公开(公告)号:US20110312136A1

    公开(公告)日:2011-12-22

    申请号:US13223940

    申请日:2011-09-01

    IPC分类号: H01L21/336

    摘要: A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.

    摘要翻译: 一种紧凑的半导体结构,其包括至少一个位于半导体衬底的表面之上和之中的FET,其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。 在一些实施例中,有序的纳米尺寸图案在垂直于电流的方向上定向。 在这样的实施例中,FET具有长的沟道长度。 在其他实施例中,有序的纳米尺寸图案在平行于电流流动的方向上取向。 在这样的实施例中,FET具有宽的通道宽度。 在另一个实施例中,一个有序的纳米尺寸图案在垂直于电流的方向上定向,而另一个有序的纳米尺寸图案在平行于电流的方向上取向。 在这样的实施例中,提供具有长沟道长度和宽沟道宽度的FET。

    THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR
    47.
    发明申请
    THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR 有权
    具有反向嵌入式应力的薄通道器件和制造方法

    公开(公告)号:US20110291189A1

    公开(公告)日:2011-12-01

    申请号:US12789699

    申请日:2010-05-28

    IPC分类号: H01L29/786 H01L21/336

    摘要: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.

    摘要翻译: 用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。 可移除的掩埋层设置在第二半导体层上或第二半导体层中。 在第一半导体层上形成具有侧面间隔物的栅极结构。 在源区和漏区的区域中形成凹陷到可移除的掩埋层。 蚀刻掉可移除的掩埋层,以在栅极结构下面的介电层下方形成底切。 在底切中形成应力层,形成源区和漏区。

    MOSFETs WITH REDUCED CONTACT RESISTANCE
    48.
    发明申请
    MOSFETs WITH REDUCED CONTACT RESISTANCE 有权
    具有降低接触电阻的MOSFET

    公开(公告)号:US20110221003A1

    公开(公告)日:2011-09-15

    申请号:US12719934

    申请日:2010-03-09

    摘要: A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.

    摘要翻译: 提供了形成具有降低的接触电阻的场效应晶体管的方法和结构。 降低的接触电阻由金属半导体合金接触电阻降低和导电填充通孔接触 - 金属半导体合金接触电阻表现出来。 在本公开内容中通过纹理化晶体管的源极区域和/或晶体管的漏极区域的表面来实现降低的接触电阻。 通常,在本公开内容中,源极区域和漏极区域都被纹理化。 与包括平坦源极区域和/或平坦漏极区域的常规晶体管相比,纹理化源极区域和/或织构化漏极区域具有增加的面积。 在源极区域的纹理表面和/或漏极区域的纹理化表面上形成金属半导体合金,例如硅化物。 在金属半导体合金的顶部形成导电填充的通孔接触。

    Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
    49.
    发明授权
    Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers 有权
    使用不同种类的应力层来增强nFET和pFET性能的结构和方法

    公开(公告)号:US08008724B2

    公开(公告)日:2011-08-30

    申请号:US10695748

    申请日:2003-10-30

    IPC分类号: H01L23/62

    摘要: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

    摘要翻译: 在制造互补的金属氧化物半导体(CMOS)场效应晶体管(包括nMOS和pMOS晶体管)的情况下,通过使用在nMOS或pMOS晶体管(或两者)上分层各种应力薄膜来增强或调节载流子迁移率, 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此,单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率,从而提高CMOS器件和集成电路的性能。

    CMOS CIRCUIT WITH LOW-K SPACER AND STRESS LINER
    50.
    发明申请
    CMOS CIRCUIT WITH LOW-K SPACER AND STRESS LINER 有权
    具有低K间距和应力衬里的CMOS电路

    公开(公告)号:US20110175169A1

    公开(公告)日:2011-07-21

    申请号:US12688471

    申请日:2010-01-15

    IPC分类号: H01L27/092 H01L21/8238

    摘要: The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of first semiconductor devices and a second plurality of semiconductor devices is provided, in which each of the first semiconductor devices are separated by a first pitch and each of the second semiconductor devices are separated by a second pitch. The first pitch separating the first semiconductor devices is less than the second pitch separating the second semiconductor devices. A low-k dielectric spacer is formed adjacent to gate structures of the first semiconductor devices. A stress inducing liner is formed on the second semiconductor devices.

    摘要翻译: 本公开提供了一种形成多个半导体器件的方法,其中根据分离半导体器件的间距,将低k电介质间隔物和应力诱导衬片施加到半导体器件。 在一个实施例中,提供了第一多个第一半导体器件和第二多个半导体器件,其中第一半导体器件中的每一个被第一间距分开,并且每个第二半导体器件分开第二间距。 分离第一半导体器件的第一节距小于分离第二半导体器件的第二节距。 在第一半导体器件的栅极结构附近形成低k电介质隔离物。 在第二半导体器件上形成应力诱导衬垫。