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公开(公告)号：US09379538B2
公开(公告)日：2016-06-28
申请号：US14357724
申请日：2012-11-09
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Guoding Dai , Xiaohui Ma , ChaoYao Xue , Jian Ou , Jing Lu
Abstract: An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage protection function.
Abstract translation: 一种用于功率因数校正的输出过压保护电路，包括芯片外部补偿网络，芯片外部电阻分压网络，静态过电压检测电路，动态过电压检测电路和比较电路; 芯片外部补偿网络连接在芯片外部电阻分压网络和动态过压检测电路之间，芯片外部补偿网络将动态过电压信号转换转换为动态电流信号，并将其传送到动态过电压 检测电路，动态过电压检测电路检测动态电流信号，最终产生动态过电压信号（DYOVP）; 动态过电压信号（DYOVP）被输入到比较电路中，其将动态过电压信号（DYOVP）转换为与参考电压相比的电压，并输出过压控制信号（OVP），以便 实现动态过压保护功能。
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公开(公告)号：US20150354945A1
公开(公告)日：2015-12-10
申请号：US14762837
申请日：2013-12-31
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Wei Huang
CPC classification number: G03F7/70625 , G01B11/02 , H01L22/12 , H01L23/544
Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.
Abstract translation: 提供了划线槽的带宽的测试结构，该结构包括彼此垂直的第一隔离线（232）和第二隔离线（234），测试结构还包括第一场区域图案 220），第一场区域图案（220）包括两个图形，两个图形各自位于第一隔离线（232）的一侧并且彼此相对。 还公开了划线槽的带宽的测试方法。 模拟LOCOS结构的场氧化物区域的图形被提供在隔离线的两侧，人造地生成步骤，通过光刻形成的小尺寸源区域上的多晶硅栅极图形可以通过在线测试带宽或 在线显示和检查条带宽度，因此可以知道模具的实际情况，可以立即发现由基板的反射引起的多晶硅栅极的宽度和形态异常。
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43.发明授权公开(公告)号：US09190897B2
公开(公告)日：2015-11-17
申请号：US14358566
申请日：2012-11-09
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Guoding Dai , Yue Chen , Xiaohui Ma , Hui Han , Renyue Ma
IPC: G05F3/02 , H02M1/42 , H03K17/687 , H03K17/16 , H03K17/0412 , H03K17/615 , H02M1/08 , H02M1/12 , H02M1/38 , H02M1/44
CPC classification number: H02M1/4208 , H02M1/08 , H02M1/12 , H02M1/38 , H02M1/42 , H02M1/44 , H03K17/0412 , H03K17/162 , H03K17/615 , H03K17/687 , H03K17/6877 , H03K2217/0081 , Y02B70/12 , Y02P80/112
Abstract: A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a Darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range. Adding dead time control into the level shift circuit not only prevents the momentary heavy-current from a power supply to the ground during the level conversion process, but also reduces the static power consumption of the drive circuit.
Abstract translation: 一种应用于功率因数校正器的高压大电流驱动电路，包括电流镜电路（1），电平移位电路（3），高电压预调制电路（2），死区时间控制电路 （4）和大电流输出级（5）; 大电流输出级采用达林顿输出级结构，以增加驱动电路的最大工作频率。 使用稳压二极管的稳定的击穿电压特性来确保驱动电路在安全电压范围内工作。 在电平转换电路中加入死区时间控制不仅可以防止在电平转换过程中瞬间的大电流来自地电源，而且可以降低驱动电路的静态功耗。
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公开(公告)号：US12183818B2
公开(公告)日：2024-12-31
申请号：US17417677
申请日：2019-12-23
Applicant: SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Weifeng Sun , Rongcheng Lou , Kui Xiao , Feng Lin , Jiaxing Wei , Sheng Li , Siyang Liu , Shengli Lu , Longxing Shi
Abstract: A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.
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公开(公告)号：US20240282765A1
公开(公告)日：2024-08-22
申请号：US18567101
申请日：2022-06-15
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Lu HUANG , Yong HUANG , Yan YAN , Wanyi ZHOU , Lin WU , Cheng ZHOU , Haili SHI
CPC classification number: H01L27/0262 , H01L27/0274 , H01L29/7436
Abstract: The present disclosure provides a GGNMOS transistor structure, an ESD protection device, and an ESD protection circuit. The GGNMOS transistor structure can increase a capability of the ESD protection device to discharge an ESD current per unit size under the action of a P-N-P-N parasitic thyristor formed by an N-potential well, a P-type heavily doped region, and an N-type heavily doped region; the GGNMOS transistor structure can limit a transient peak current of ESD under the action of an equivalent resistor formed by an N-potential well, so that respective GGNMOS transistors of the ESD protection device can conduct uniformly, improving the reliability of the ESD protection circuit.
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Patent Agency Ranking
公开(公告)号：US20240222478A1
公开(公告)日：2024-07-04
申请号：US18558422
申请日：2022-01-24
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
IPC: H01L29/739 , H01L27/07 , H01L29/423 , H01L29/866
CPC classification number: H01L29/7394 , H01L27/0727 , H01L29/4236 , H01L29/866
Abstract: A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.
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公开(公告)号：US12009129B2
公开(公告)日：2024-06-11
申请号：US18308399
申请日：2023-04-27
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Congying Dong
IPC: H01F17/00 , H01L23/522
CPC classification number: H01F17/0013 , H01L23/5227 , H01F2017/0086
Abstract: A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.
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公开(公告)号：US11894458B2
公开(公告)日：2024-02-06
申请号：US17762206
申请日：2020-09-25
Applicant: SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Jiaxing Wei , Qichao Wang , Kui Xiao , Dejin Wang , Li Lu , Ling Yang , Ran Ye , Siyang Liu , Weifeng Sun , Longxing Shi
IPC: H01L29/78
CPC classification number: H01L29/7825
Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
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公开(公告)号：US20230036341A1
公开(公告)日：2023-02-02
申请号：US17789628
申请日：2020-09-04
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Jingchuan ZHAO , Zhili ZHANG , Sen ZHANG
Abstract: Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.
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公开(公告)号：US11515395B2
公开(公告)日：2022-11-29
申请号：US17624336
申请日：2020-09-25
Applicant: SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD
Inventor： Siyang Liu , Ningbo Li , Dejin Wang , Kui Xiao , Chi Zhang , Sheng Li , Xinyi Tao , Weifeng Sun , Longxing Shi
IPC: H01L29/872 , H01L29/20 , H01L29/66 , H01L21/02 , H01L29/06 , H01L29/861
Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.
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