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    Memory devices including barrier layers and methods of manufacturing the same
    41.
    发明申请
    Memory devices including barrier layers and methods of manufacturing the same 有权
    存储器件包括阻挡层及其制造方法

    公开(公告)号：US20060077743A1

    公开(公告)日：2006-04-13

    申请号：US11245426

    申请日：2005-10-07

    申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

    发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

    IPC分类号： G11C7/00

    CPC分类号： H01L21/28273 ,  H01L29/513 ,  H01L29/7881

    摘要： Memory devices and methods of manufacturing the same are provided. Memory devices may include a substrate, a source region and a drain region and a gate structure. The gate structure may be in contact with the source and drain regions, and may include a barrier layer. The barrier layer may be formed of at least two layers. The at least two layers may have different bandgap energies.

    摘要翻译： 提供了存储器件及其制造方法。 存储器件可以包括衬底，源极区域和漏极区域以及栅极结构。 栅极结构可以与源极和漏极区域接触，并且可以包括阻挡层。 阻挡层可以由至少两层形成。 至少两层可能具有不同的带隙能量。

    SONOS type memory device
    42.
    发明申请
    SONOS type memory device 失效
    SONOS型存储设备

    公开(公告)号：US20050205920A1

    公开(公告)日：2005-09-22

    申请号：US11070090

    申请日：2005-03-03

    申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Dong-joon Ma ,  Sung-kyu Choi

    发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Dong-joon Ma ,  Sung-kyu Choi

    IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L31/119

    CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28282 ,  H01L21/31616 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/792

    摘要： A SONOS type memory includes a semiconductor substrate, first and second impurity regions in the semiconductor substrate doped with impurity ions of a predetermined conductivity, separated a predetermined distance from each other, a channel region between the first and second impurity regions, and a data storage type stack on the semiconductor substrate between the first and second impurity regions. The data storage type stack includes a tunneling oxide layer, a memory node layer for storing data, a blocking oxide layer, and an electrode layer, which are sequentially formed. A dielectric constant of the memory node layer is higher than dielectric constants of the tunneling and the blocking oxide layers, and a band offset of the memory node layer is lower than band offsets of the tunneling and the blocking oxide layers. The tunneling oxide layer and the blocking oxide layer are high dielectric insulating layers.

    摘要翻译： SONOS型存储器包括半导体衬底，掺杂有预定电导率的杂质离子的半导体衬底中的第一和第二杂质区，彼此隔开预定距离，第一和第二杂质区之间的沟道区，以及数据存储 在第一和第二杂质区之间的半导体衬底上。 数据存储型堆叠包括依次形成的隧道氧化物层，用于存储数据的存储节点层，阻挡氧化物层和电极层。 存储节点层的介电常数高于隧道和阻塞氧化物层的介电常数，并且存储器节点层的带偏移低于隧道和阻塞氧化物层的带偏移。 隧道氧化物层和阻挡氧化物层是高介电绝缘层。

    Single electron transistor using porous silicon
    44.
    发明授权
    Single electron transistor using porous silicon 有权
    单电子晶体管采用多孔硅

    公开(公告)号：US06414333B1

    公开(公告)日：2002-07-02

    申请号：US09522603

    申请日：2000-03-10

    申请人： Jo-won Lee ,  Chung-woo Kim ,  Byong-man Kim ,  Moon-kyung Kim

    发明人： Jo-won Lee ,  Chung-woo Kim ,  Byong-man Kim ,  Moon-kyung Kim

    IPC分类号： H01L2906

    CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/16 ,  Y10S438/96 ,  Y10S977/937

    摘要： A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.

    摘要翻译： 提供了通过使用通过电化学蚀刻硅获得的尺寸为几十纳米的多孔硅制造的使用多孔硅的单电子晶体管及其制造方法。 在使用多孔硅的单电子晶体管中，通过使用HF在其下部电化学蚀刻其下部具有二氧化硅（SiO 2）的绝缘体上硅（SOI）衬底，制造每个具有5nm或更小直径的硅孔。 的溶液，并且用作单电子晶体管的岛。 此外，源极和漏极由其上沉积有金属的硅或掺杂有杂质的硅形成。 因此，岛和隧道壁垒的形成是容易的，批量生产是可能的，并且可以通过氧化来控制岛的尺寸，使得能够容易地制造能够在室温下操作的单电子晶体管。

    MULTI-BIT NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND METHOD OF FABRICATING THE SAME
    47.
    发明申请
    MULTI-BIT NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND METHOD OF FABRICATING THE SAME 失效
    多位非易失性存储器件，其操作方法及其制造方法

    公开(公告)号：US20090010058A1

    公开(公告)日：2009-01-08

    申请号：US12209735

    申请日：2008-09-12

    申请人： Soo-doo CHAE ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

    发明人： Soo-doo CHAE ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

    摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

    摘要翻译： 可以提供多位非易失性存储器件及其操作和制造方法。 存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。 此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。 第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

    Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices
    50.
    发明授权
    Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices 有权
    氧化硅氧化物半导体（SONOS）存储器件的编程方法

    公开(公告)号：US07349262B2

    公开(公告)日：2008-03-25

    申请号：US11432375

    申请日：2006-05-12

    申请人： Youn-seok Jeong ,  Chung-woo Kim ,  Hee-soon Chae ,  Ju-hyung Kim ,  Jeong-hee Han ,  Jae-woong Hyun

    发明人： Youn-seok Jeong ,  Chung-woo Kim ,  Hee-soon Chae ,  Ju-hyung Kim ,  Jeong-hee Han ,  Jae-woong Hyun

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0466 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004

    摘要： A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.

    摘要翻译： 提供了一种编程氧化硅氮氧化物半导体（SONOS）存储器件的方法。 SONOS存储器件包括衬底，在衬底上间隔开的第一和第二杂质区，在第一和第二杂质区之间的衬底上形成的栅氧化层，在栅极氧化物层上形成的阱层，形成在绝缘层上的绝缘层 陷阱层和形成在绝缘层上的栅电极。 对SONOS设备进行编程的方法包括：通过向第一杂质区施加第一电压，向栅电极施加第一电压，向第二杂质区施加第二电压，将数据写入SONOS存储器件，其中第二电压为 负电压。