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    Memory Device Having a Delay Locked Loop and Multiple Power Modes
    41.
    发明申请
    Memory Device Having a Delay Locked Loop and Multiple Power Modes 审中-公开
    具有延迟锁定环路和多个功率模式的存储器件

    公开(公告)号：US20080002516A1

    公开(公告)日：2008-01-03

    申请号：US11856661

    申请日：2007-09-17

    申请人： Ely Tsern ,  Richard Barth ,  Craig Hampel ,  Donald Stark

    发明人： Ely Tsern ,  Richard Barth ,  Craig Hampel ,  Donald Stark

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G11C7/1039 ,  G11C7/1072 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： A single chip dynamic random access memory has a memory core, including dynamic random access memory cells, and a clock receiver circuit to receive an external clock signal. A delay locked loop circuit is coupled to the clock receiver circuit. In a first power mode, the delay locked loop circuit and the clock receiver circuit are turned on. Power consumption in the first power mode is less than that consumed while in an active mode. In a second power mode, the delay locked loop circuit is turned off. The memory is configured to receive a command that specifies a power down mode, to turn off the delay locked loop circuit in response to the command that specifies the power down mode, and to operate the memory device in a standby power mode. The delay locked loop circuit and the clock receiver circuit are turned on in a standby mode.

    摘要翻译： 单芯片动态随机存取存储器具有存储核心，包括动态随机存取存储器单元和用于接收外部时钟信号的时钟接收器电路。 延迟锁定环电路耦合到时钟接收器电路。 在第一功率模式中，延迟锁定环电路和时钟接收器电路被接通。 在第一个功率模式下的功耗小于活动模式时消耗的功耗。 在第二功率模式中，延迟锁定环电路被关断。 存储器被配置为接收指定掉电模式的命令，以响应于指定掉电模式的命令来关闭延迟锁定环电路，并且在待机电源模式下操作存储器件。 延迟锁定环电路和时钟接收器电路在待机模式下导通。

    COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
    42.
    发明申请
    COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
    通信通道校准条件

    公开(公告)号：US20070280393A1

    公开(公告)日：2007-12-06

    申请号：US11754102

    申请日：2007-05-25

    申请人： Frederick Ware ,  Richard Perego ,  Craig Hampel

    发明人： Frederick Ware ,  Richard Perego ,  Craig Hampel

    IPC分类号： H04L7/00

    CPC分类号： H04L1/242 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12 ,  H04L27/00

    摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

    摘要翻译： 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

    Clocked Memory System with Termination Component
    43.
    发明申请
    Clocked Memory System with Termination Component 有权
    带终端组件的定时存储系统

    公开(公告)号：US20070247935A1

    公开(公告)日：2007-10-25

    申请号：US11767983

    申请日：2007-06-25

    申请人： Frederick Ware ,  Ely Tsern ,  Richard Perego ,  Craig Hampel

    发明人： Frederick Ware ,  Ely Tsern ,  Richard Perego ,  Craig Hampel

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1039 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048

    摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.

    摘要翻译： 一种具有第一和第二存储器件和终端部件的存储器系统。 第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线， 到第二存储设备。 控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。 提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

    Memory Device Having a Configurable Oscillator for Refresh Operation
    44.
    发明申请
    Memory Device Having a Configurable Oscillator for Refresh Operation 有权
    具有用于刷新操作的可配置振荡器的存储器件

    公开(公告)号：US20070147155A1

    公开(公告)日：2007-06-28

    申请号：US11562856

    申请日：2006-11-22

    申请人： Ely Tsern ,  Richard Barth ,  Paul Davis ,  Craig Hampel

    发明人： Ely Tsern ,  Richard Barth ,  Paul Davis ,  Craig Hampel

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40618 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4061 ,  G11C2211/4067

    摘要： A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operation is selected such that the refresh frequency is minimized to conserve power consumed by the memory device while being sufficient to refresh the rows of the memory cells.

    摘要翻译： 动态随机存取存储器件包括一组动态存储器单元。 响应于接收到自刷新命令，设备通过刷新位于每个存储体中的存储单元的行来执行刷新操作。 此外，选择刷新操作的刷新频率使得刷新频率最小化以节省存储器件消耗的功率，同时足以刷新存储器单元的行。

    Integrated Circuit Memory Device Having Delayed Write Capability
    45.
    发明申请
    Integrated Circuit Memory Device Having Delayed Write Capability 失效
    具有延迟写入能力的集成电路存储器件

    公开(公告)号：US20070147143A1

    公开(公告)日：2007-06-28

    申请号：US11681375

    申请日：2007-03-02

    申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

    发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

    摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

    摘要翻译： 集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。 器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。 在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。 在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

    Memory device having a read pipeline and a delay locked loop
    48.
    发明申请
    Memory device having a read pipeline and a delay locked loop 有权
    具有读取流水线和延迟锁定环路的存储器件

    公开(公告)号：US20050180255A1

    公开(公告)日：2005-08-18

    申请号：US11107504

    申请日：2005-04-15

    申请人： Ely Tsern ,  Richard Barth ,  Craig Hampel ,  Donald Stark

    发明人： Ely Tsern ,  Richard Barth ,  Craig Hampel ,  Donald Stark

    IPC分类号： G06F1/32 ,  G06F9/38 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G11C7/1039 ,  G11C7/1072 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.

    摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。 时钟接收器电路接收外部时钟信号。 控制接口接收指定对存储器件的读取操作的命令。 数据接口在存储器件和外部信号线组之间传送数据。 延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。 读取管线电路将从存储器核心访问的读取数据提供给数据接口。 响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。