公开(公告)号：US20050151224A1

公开(公告)日：2005-07-14

申请号：US10910318

申请日：2004-08-04

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/288 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/532 ,  H01L29/00

CPC classification number: H01L23/5226 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

Abstract translation: 半导体器件具有半导体衬底，形成在半导体衬底的表面上的第一绝缘膜，形成在第一绝缘膜中的第一凹槽，形成在除了顶部周边区域之外的第一绝缘膜的内表面上的第一阻挡膜 形成在第一沟槽中的第一导电膜和形成在第一导电膜的上表面和顶周边区域上的覆盖膜和第一阻挡膜的上表面。 第一导电膜包括铜。

公开(公告)号：US20050087872A1

公开(公告)日：2005-04-28

申请号：US10766739

申请日：2004-01-29

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The wiring structure of a semiconductor device of the invention enhances the dielectric strength of the wirings and reduces the capacitance across the wirings, by preventing a diffusion of the wiring material. The wiring structure includes a first insulating film, plural wiring films, plural barrier films, and plural cap films. The first insulating film has plural grooves formed thereon, and has an interface in the horizontal direction between the adjoining grooves. The wiring films are formed to protrude from the interface each by the grooves of the first insulating film. The barrier films are formed on the bottoms of the wiring films, and also on side faces of the wiring films to a height exceeding the interface. The cap films are formed at least on the upper faces of the wiring films, and are separated each by the grooves.

Abstract translation: 本发明的半导体器件的布线结构通过防止布线材料的扩散，增强布线的介电强度并降低布线两端的电容。 布线结构包括第一绝缘膜，多个布线膜，多个阻挡膜和多个盖膜。 第一绝缘膜具有形成在其上的多个槽，并且在相邻的槽之间具有在水平方向上的界面。 布线膜形成为从第一绝缘膜的沟槽各自的界面突出。 阻挡膜形成在布线膜的底部以及布线膜的侧面上，达到超过界面的高度。 盖膜至少形成在布线膜的上表面上，并由沟槽分开。

公开(公告)号：US06870446B2

公开(公告)日：2005-03-22

申请号：US10252105

申请日：2002-09-23

Applicant: Ryoichi Ohara ,  Kazuhide Abe ,  Takashi Kawakubo ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Ryuichi Fujimoto

Inventor： Ryoichi Ohara ,  Kazuhide Abe ,  Takashi Kawakubo ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Ryuichi Fujimoto

IPC: H03H9/00 ,  H03H9/54 ,  H03H9/58 ,  H03H9/60

CPC classification number: H03H9/605 ,  H03H9/0095 ,  H03H9/542 ,  H03H9/581 ,  H03H2009/02196

Abstract: A high frequency filter comprises thin film piezoelectric resonators connected in series between the input/output nodes, thin film piezoelectric resonators connected in parallel between the input/output nodes and a variable voltage circuit adapted to change the voltage applied to at least either the thin film piezoelectric resonators connected in series or the thin film piezoelectric resonators connected in parallel. The resonance characteristic of at least either the thin film piezoelectric resonators connected in series or the thin film piezoelectric resonator connected in parallel is shifted by changing the voltage applied by the variable voltage circuit to change the pass characteristic of the filter.

Abstract translation: 高频滤波器包括串联连接在输入/输出节点之间的薄膜压电谐振器，并联连接在输入/输出节点之间的薄膜压电谐振器和可变电压电路，可变电压电路适于改变施加到至少薄膜的电压 串联连接的压电谐振器或并联连接的薄膜压电谐振器。 串联连接的薄膜压电谐振器或并联连接的薄膜压电谐振器中的至少一个的谐振特性通过改变由可变电压电路施加的电压来改变滤波器的通过特性而被移位。

公开(公告)号：US06809604B2

公开(公告)日：2004-10-26

申请号：US10397876

申请日：2003-03-27

Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Ryuichi Fujimoto

Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Ryuichi Fujimoto

IPC: H03B532

CPC classification number: H03H9/173 ,  H03H9/0095 ,  H03H9/545 ,  H03H9/562 ,  H03H9/564 ,  H03H9/566 ,  H03H9/581 ,  H03H9/585 ,  H03H9/60 ,  H03H2009/02196

Abstract: To provide a miniaturized voltage controlled oscillator which can oscillate simultaneously a plurality of frequencies and has high stability of frequency, an excellent low phase noise, small variation per hour, and a wide frequency variable range. A thin film bulk acoustic wave resonator using single crystal ferroelectric material equal to or smaller than 10 &mgr;m in thickness whose direction of polarization is aligned to the direction of thickness is utilized as the piezoelectric member. The voltage controlled oscillator having large changing rate of the oscillation frequency of 0.01%/V or more and an extremely small phase noise is provided by changing the voltage applied to the electrodes.

Abstract translation: 为了提供能够同时振荡多个频率并且具有高的频率稳定性，优异的低相位噪声，小时变化小和宽频率可变范围的微型压控振荡器.1。一种使用单晶的薄膜体声波谐振器 作为压电部件，利用等于或小于10μm厚的偏振方向与厚度方向对准的铁电材料。 通过改变施加到电极上的电压，提供振荡频率变化率大于0.01％/ V以上且极小相位噪声的压控振荡器。

公开(公告)号：US06767812B2

公开(公告)日：2004-07-27

申请号：US09984383

申请日：2001-10-30

Applicant: Kazuhide Abe ,  Yusuke Harada

Inventor： Kazuhide Abe ,  Yusuke Harada

IPC: H01L2128

CPC classification number: C23C16/0272 ,  C23C16/14

Abstract: Before deposition of a CVD titanium film on a cobalt silicide layer, an element which reacts with titanium is provided in the cobalt silicide layer in advance. Thereafter, the CVD titanium film is deposited on the cobalt silicide using a titanium tetrachloride gas.

Abstract translation: 在将CVD钛膜沉积在硅化钴层上之前，预先在钴硅化物层中提供与钛反应的元素。 此后，使用四氯化钛气体将CVD钛膜沉积在硅化钴上。

公开(公告)号：US5889696A

公开(公告)日：1999-03-30

申请号：US45958

申请日：1998-03-23

Applicant: Takashi Kawakubo ,  Noburu Fukushima ,  Kazuhide Abe

Inventor： Takashi Kawakubo ,  Noburu Fukushima ,  Kazuhide Abe

IPC: H01L27/10 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC classification number: G11C11/22

Abstract: A semiconductor memory device is constituted by arranging a plurality of memory cells in a matrix format, each of which includes a thin-film capacitor having a ferroelectric film and a pair of electrodes facing each other via the ferroelectric film, and a transfer gate transistor connected to the thin film capacitor. A voltage corresponding to the width of a hysteresis curve obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 20% or lower of the voltage difference between the positive and negative directions in a writing operation. A remanent polarization amount obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 30% or lower of the total polarization amount obtained upon application of a voltage in the writing operation.

Abstract translation: 半导体存储器件通过以矩阵形式布置多个存储单元而构成，每个存储单元包括具有铁电膜的薄膜电容器和经由铁电体膜相互面对的一对电极，并且连接有传输栅极晶体管 到薄膜电容器。 当薄膜电容器饱和和极化时获得的滞后曲线的宽度对应的电压落在写入操作中正负方向之间的电压差的5％以上至20％以下的范围内。 当薄膜电容器饱和和极化时获得的剩余极化量落在在写入操作中施加电压时获得的总极化量的5％以上至30％以下的范围内。

公开(公告)号：US08859426B2

公开(公告)日：2014-10-14

申请号：US12170458

申请日：2008-07-10

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/768 ,  H01L21/288 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

Abstract translation: 半导体器件具有半导体衬底，形成在半导体衬底的表面上的第一绝缘膜，形成在第一绝缘膜中的第一凹槽，形成在除了顶部周边区域之外的第一绝缘膜的内表面上的第一阻挡膜 形成在第一沟槽中的第一导电膜和形成在第一导电膜的上表面和顶周边区域上的覆盖膜和第一阻挡膜的上表面。 第一导电膜包括铜。

公开(公告)号：US08513715B2

公开(公告)日：2013-08-20

申请号：US12873788

申请日：2010-09-01

Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya

Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/41758 ,  H01L29/4238 ,  H03B5/326

Abstract: According to an embodiment, the present invention provides a semiconductor device that is easily integrated with other electronic circuits and functions as an oscillator with high frequency accuracy. The semiconductor device includes: a semiconductor substrate; an element region; an element isolation region that surrounds the element region; a field effect transistor including a gate electrode that is formed on the element region, source and drain regions, and a channel region that is interposed between the source region and the drain region; gate, source, and drain terminals that are used to apply a voltage to the gate electrode, the source region, and the drain region, respectively; and an output terminal that is electrically connected to the channel region. When the threshold voltage of the field effect transistor is Vth, a gate voltage Vgs applied between the source terminal and the gate terminal and a drain voltage Vds applied between the source terminal and the drain terminal satisfy the following relationship: Vth

Abstract translation: 根据实施例，本发明提供一种与其他电子电路容易集成并且作为高频精度的振荡器起作用的半导体器件。 半导体器件包括：半导体衬底; 元素区域 围绕元件区域的元件隔离区域; 场效应晶体管，其包括形成在所述元件区域，源极和漏极区域上的栅极电极以及介于所述源极区域和所述漏极区域之间的沟道区域; 栅极，源极和漏极端子，分别用于向栅极电极，源极区域和漏极区域施加电压; 以及电连接到沟道区的输出端子。 当场效应晶体管的阈值电压为Vth时，施加在源极端子和栅极端子之间的栅极电压Vgs和施加在源极端子和漏极端子之间的漏极电压Vds满足以下关系：Vth

公开(公告)号：US20120200357A1

公开(公告)日：2012-08-09

申请号：US13424591

申请日：2012-03-20

Applicant: Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya

Inventor： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya

IPC: H03F3/45

CPC classification number: H03F3/19 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4238 ,  H03F3/245

Abstract: A power amplifier according to the embodiments includes: a silicon substrate; an input terminal configured to receive an input of a RF signal; a power dividing unit configured to divide the RF signal into a first signal and a second signal; a phase modulating unit configured to modulate a phase of the second signal; an N well formed in the silicon substrate; a P well formed in the N well and configured to receive an input of the second signal of a modulated phase; a gate insulating film formed on the P well; a gate electrode formed on the gate insulating film and configured to receive an input of the first signal; source and drain electrodes formed on both sides of the gate electrode in the silicon substrate; and an output terminal configured to output a RF signal obtained from the drain electrode.

Abstract translation: 根据实施例的功率放大器包括：硅衬底; 输入终端，被配置为接收RF信号的输入; 功率分配单元，被配置为将RF信号划分为第一信号和第二信号; 相位调制单元，被配置为调制所述第二信号的相位; 在硅衬底中形成N阱; P阱形成在N阱中并且被配置为接收调制相位的第二信号的输入; 在P阱上形成栅极绝缘膜; 栅电极，形成在所述栅极绝缘膜上并被配置为接收所述第一信号的输入; 源极和漏极形成在硅衬底中的栅电极的两侧; 以及输出端子，被配置为输出从漏电极获得的RF信号。

公开(公告)号：US20120061768A1

公开(公告)日：2012-03-15

申请号：US13050545

申请日：2011-03-17

Applicant: Tadahiro SASAKI ,  Kazuhide Abe ,  Atsuko Iida ,  Kazuhiko Itaya

Inventor： Tadahiro SASAKI ,  Kazuhide Abe ,  Atsuko Iida ,  Kazuhiko Itaya

IPC: H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823493 ,  H01L27/0207 ,  H01L27/0922 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78

Abstract: According to an embodiment, a power amplifier is provided with at least one first growth ring gate structure and multiple second growth ring gate structures. The first growth ring gate structure is bounded by a semiconductor layer and performs a power amplification operation. The multiple second growth ring gate structures are bounded by the semiconductor layer and are arranged adjacently around the first growth ring gate structure in a surrounding manner. When the first growth ring gate structure performs a power amplification operation, the multiple second growth ring gate structures are depleted by applying a reverse bias to the multiple second growth ring gate structures whereby the depleted multiple second growth ring gate structures isolate the first growth ring gate structure from a surrounding portion.

Abstract translation: 根据实施例，功率放大器设置有至少一个第一增长环栅极结构和多个第二增长环栅极结构。 第一生长环栅极结构由半导体层限制并进行功率放大操作。 多个第二生长环形栅极结构由半导体层限制，并且以周围的方式围绕第一生长环栅极结构相邻布置。 当第一生长环栅极结构执行功率放大操作时，通过向多个第二生长环栅极结构施加反向偏压来耗尽多个第二生长环栅结构，由此耗尽的多个第二生长环栅极结构将第一生长环栅极隔离 结构从周围部分。