公开(公告)号：US09685206B2

公开(公告)日：2017-06-20

申请号：US13948557

申请日：2013-07-23

Applicant: Myung-Hoon Choi ,  Jae-Yong Jeong ,  Ki-Tae Park

Inventor： Myung-Hoon Choi ,  Jae-Yong Jeong ,  Ki-Tae Park

IPC: G11C7/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/44 ,  G11C29/02 ,  G11C16/00

CPC classification number: G11C7/1057 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44

Abstract: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

公开(公告)号：US09129663B2

公开(公告)日：2015-09-08

申请号：US14108417

申请日：2013-12-17

Applicant: Ki-Tae Park

Inventor： Ki-Tae Park

IPC: G11C5/02 ,  G11C8/12 ,  G11C5/14 ,  G11C7/20

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/025 ,  G11C5/143 ,  G11C7/20

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips

Abstract translation: 半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。 各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个 设备芯片

公开(公告)号：US08791370B2

公开(公告)日：2014-07-29

申请号：US12710926

申请日：2010-02-23

Applicant: Tae Ki Hong ,  Dong Guk Jo ,  Han Mo Koo ,  Jun Young Lim ,  Ki Tae Park ,  Sang Ki Cho ,  Dae Sung Yoo ,  Nak Ho Song ,  Joo Chul Kim ,  Jae Sung Jo

Inventor： Tae Ki Hong ,  Dong Guk Jo ,  Han Mo Koo ,  Jun Young Lim ,  Ki Tae Park ,  Sang Ki Cho ,  Dae Sung Yoo ,  Nak Ho Song ,  Joo Chul Kim ,  Jae Sung Jo

IPC: H05K1/11 ,  H01L23/00

CPC classification number: H01L24/50 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/37001 ,  H05K1/11 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The present invention relates to a carrier tape for TAB-package and a manufacturing method thereof, wherein a TAB tape including a wiring pattern and a metal plating layer formed on a base film comprises a transfer area including a row of sprocket holes arranged along the edges of the base film at predetermined intervals, and wherein the transfer area includes an exposure area from which the base film is exposed, such that the present invention has an advantageous effect in that no Cu layer or a metal layer exists at a portion of the sprocket holes from which friction is generated by a driving roller during assembly work between a drive IC and chips/drive IC and panel to dispense with generation of foreign objects such as Cu particles, thereby enhancing reliability of the product.

Abstract translation: 本发明涉及一种用于TAB封装的载带及其制造方法，其中包括布线图案和形成在基膜上的金属镀层的TAB带包括传送区域，其包括沿着边缘布置的一排链轮孔 并且其中转印区域包括暴露于基膜的曝光区域，使得本发明具有如下优点：在链轮的一部分处不存在Cu层或金属层 在驱动IC和芯片/驱动IC和面板之间的组装工作期间由驱动辊产生摩擦的孔，以省去诸如Cu颗粒的异物的产生，从而提高产品的可靠性。

公开(公告)号：US20140169101A1

公开(公告)日：2014-06-19

申请号：US14187362

申请日：2014-02-24

Applicant: Yoon Hee Choi ,  Ki Tae Park ,  Bo Geun Kim

Inventor： Yoon Hee Choi ,  Ki Tae Park ,  Bo Geun Kim

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C16/26 ,  G11C16/30

Abstract: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line.

Abstract translation: 公开了一种在非易失性存储器件中生成诸如读取电压的补偿工作电压的方法以及相关的非易失性存储器件。 响应于一个或多个存储器单元条件（诸如所选存储器单元的温度变化，编程数据状态或物理位置，所选择的存储器单元的页面信息或所选择的字线的位置）来补偿工作电压。

公开(公告)号：US08644066B2

公开(公告)日：2014-02-04

申请号：US12620907

申请日：2009-11-18

Applicant: Ki Tae Park

Inventor： Ki Tae Park

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G06F11/141 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/00 ,  G11C2211/5646

Abstract: Methods of programming nonvolatile memory devices include programming a plurality of nonvolatile multi-state memory cells in the non-volatile memory device with state-converted data derived from non-state-converted data. This state-converted data may be associated with a greater number of erased states relative to the non-state-converted data, when programmed into the plurality of nonvolatile memory cells. The methods also include generating a flag having a value that indicates which ones of the plurality of nonvolatile memory cells have been programmed with data that is swapped with data in other ones of the plurality of nonvolatile memory cells. This flag may also be programmed into the nonvolatile memory device. Operations may also be performed to read the state-converted data (and flag) from the plurality of nonvolatile memory cells and then decode the state-converted data into the non-state-converted data, based on the value of the flag.

Abstract translation: 非易失性存储器件的编程方法包括使用从非状态转换数据导出的状态转换数据来编程非易失性存储器件中的多个非易失性多态存储器单元。 当被编程到多个非易失性存储器单元中时，该状态转换的数据可以与相对于非状态转换的数据的更多数量的擦除状态相关联。 该方法还包括产生一个标志，该标志具有指示多个非易失性存储单元中的哪一个已被编程的数据与多个非易失性存储器单元中的其他非易失性存储器单元中的数据进行交换。 该标志也可以被编程到非易失性存储器件中。 还可以执行操作以从多个非易失性存储器单元读取状态转换的数据（和标志），然后基于标志的值将状态转换的数据解码为非状态转换的数据。

公开(公告)号：US08607120B2

公开(公告)日：2013-12-10

申请号：US12726963

申请日：2010-03-18

Applicant: Youngsun Song ,  Ki Tae Park

Inventor： Youngsun Song ,  Ki Tae Park

IPC: G11C29/00

CPC classification number: H03M13/13 ,  G06F11/1072 ,  H03M13/2906 ,  H03M13/356

Abstract: A semiconductor memory device for performing additional error correction code (ECC) correction according to a cell pattern and an electronic system including the same are provided. The semiconductor memory device includes a memory cell array configured to store user data; and an ECC engine configured to perform first ECC encoding on the user data, output a result of the first ECC encoding as ECC information, detect a predetermined cell pattern based on the user data, and additionally perform second ECC encoding on data of a cell corresponding to the predetermined cell pattern detected. Accordingly, data errors that may occur due to a certain cell pattern are prevented.

Abstract translation: 提供了一种用于根据单元图案执行附加纠错码（ECC）校正的半导体存储器件和包括其的电子系统。 半导体存储器件包括：存储单元阵列，用于存储用户数据; 以及ECC引擎，被配置为对所述用户数据执行第一ECC编码，将所述第一ECC编码的结果作为ECC信息输出，基于所述用户数据检测预定的小区模式，并且还对相应的小区的数据进行第二ECC编码 到检测到的预定细胞图案。 因此，可以防止由于某个单元图案而发生的数据错误。

公开(公告)号：US08539138B2

公开(公告)日：2013-09-17

申请号：US12961791

申请日：2010-12-07

Applicant: Min Seok Kim ,  Ki Tae Park

Inventor： Min Seok Kim ,  Ki Tae Park

IPC: G06F12/02

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2211/5621

Abstract: A flash memory device performs a program operation using an incremental step pulse programming (ISPP) scheme comprising a plurality of program loops. In each of the program loops, a program pulse operation is performed to increase the threshold voltages of selected memory cells, and a program verify operation is performed to verify a program status of the selected memory cells. The program verify operation can be selectively skipped in some program loops based on a voltage increment of one or more of the program pulse operations, an amount by which threshold voltages of the selected memory cells are to be increased in the ISPP scheme, or a total number of program loops of the ISPP scheme.

Abstract translation: 闪存器件使用包括多个程序循环的增量步进脉冲编程（ISPP）方案来执行编程操作。 在每个程序循环中，执行编程脉冲操作以增加所选存储单元的阈值电压，并且执行程序验证操作以验证所选存储单元的程序状态。 可以基于一个或多个编程脉冲操作的电压增量在一些程序循环中选择性地跳过程序验证操作，在ISPP方案中所选择的存储器单元的阈值电压将增加的量，或总共 ISPP方案的程序循环数。

公开(公告)号：US08536026B2

公开(公告)日：2013-09-17

申请号：US11822185

申请日：2007-07-03

Applicant: Hee Seok Park ,  Gil Han Park ,  Sang Duk Yoo ,  Young Min Park ,  Hak Hwan Kim ,  Seon Young Myoung ,  Sang Bum Lee ,  Ki Tae Park ,  Myoung Sik Jung ,  Kyeong Ik Min

Inventor： Hee Seok Park ,  Gil Han Park ,  Sang Duk Yoo ,  Young Min Park ,  Hak Hwan Kim ,  Seon Young Myoung ,  Sang Bum Lee ,  Ki Tae Park ,  Myoung Sik Jung ,  Kyeong Ik Min

IPC: H01L29/24 ,  H01L21/36 ,  H01L33/00

CPC classification number: C30B25/04 ,  C30B25/02 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/24

Abstract: A method for selectively growing a nitride semiconductor, in which a mask is formed, with an opening formed therein, on a nitride semiconductor layer. A nitride semiconductor crystal is selectively grown on a portion of the nitride semiconductor layer exposed through the opening in the mask, the nitride semiconductor crystal shaped as a hexagonal pyramid and having crystal planes inclined with respect to a top surface of the nitride semiconductor. Here, the nitride semiconductor crystal has at least one intermediate stress-relieving area having crystal planes inclined at a greater angle than those of upper and lower areas of the nitride semiconductor crystal, the intermediate stress-relieving area relieving stress which occurs from continuity in the inclined crystal planes.

Abstract translation: 一种在氮化物半导体层上选择性地生长其中形成掩模的氮化物半导体，其中形成有开口的方法。 氮化物半导体晶体选择性地生长在通过掩模中的开口暴露的氮化物半导体层的一部分上，氮化物半导体晶体形状为六角锥，并具有相对于氮化物半导体的顶表面倾斜的晶面。 这里，氮化物半导体晶体具有至少一个具有比氮化物半导体晶体的上部和下部区域倾斜角度大的晶面的中间应力消除区域，由中间应力消除区域的连续性产生的中间应力消除面积减轻应力 斜晶面。

公开(公告)号：USD680228S1

公开(公告)日：2013-04-16

申请号：US29412449

申请日：2012-02-03

Applicant: Eui-Yul Choi ,  Kie-Bong Nahm ,  Byeong-Chul Kim ,  Ki-Tae Park ,  Cheol-Min Kim

Designer： Eui-Yul Choi ,  Kie-Bong Nahm ,  Byeong-Chul Kim ,  Ki-Tae Park ,  Cheol-Min Kim

公开(公告)号：US08315105B2

公开(公告)日：2012-11-20

申请号：US13153285

申请日：2011-06-03

Applicant: Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

Abstract translation: 一种在非易失性存储器件中进行后编程的擦除方法。 该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。 第一电压与第二电压不同。