公开(公告)号：US20050189993A1

公开(公告)日：2005-09-01

申请号：US11005603

申请日：2004-12-06

Applicant: Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

Inventor： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC: H03G1/00 ,  H03G3/00 ,  H03G3/30 ,  H03G5/10 ,  H03H11/24

CPC classification number: H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract translation: 电路从集成电路可编程增益衰减器中的信号路径中去除开关。 可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。 这种开关可能在信号中引入非线性。 通过将开关与信号路径隔离，可以提高PGA的线性度。

公开(公告)号：US20050153677A1

公开(公告)日：2005-07-14

申请号：US11050107

申请日：2005-02-04

Applicant: Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr

Inventor： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr

IPC: H01F17/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08 ,  H03B5/12 ,  H03B5/36 ,  H03D3/18 ,  H03D7/16 ,  H03D7/18 ,  H03G1/00 ,  H03H11/12 ,  H03J1/00 ,  H03J3/04 ,  H03J3/08 ,  H03J3/18 ,  H03L7/10 ,  H03L7/23 ,  H04B1/18 ,  H04B1/26 ,  H04B15/00

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。

公开(公告)号：US20050107055A1

公开(公告)日：2005-05-19

申请号：US11020478

申请日：2004-12-27

Applicant: Klaas Bult ,  Ramon Gomez

Inventor： Klaas Bult ,  Ramon Gomez

IPC: H01F17/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08 ,  H03B5/12 ,  H03B5/36 ,  H03D3/18 ,  H03D7/16 ,  H03D7/18 ,  H03G1/00 ,  H03H11/12 ,  H03J1/00 ,  H03J3/04 ,  H03J3/08 ,  H03J3/18 ,  H03L7/10 ,  H03L7/23 ,  H04B17/02 ,  H04B1/06 ,  H04B1/10

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。

公开(公告)号：US06809667B2

公开(公告)日：2004-10-26

申请号：US10688122

申请日：2003-10-17

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M106

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter. A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

Abstract translation: 提供了一种用于减少模数转换器中连续的单元格对的输出之间的不匹配的电路。 电压输入装置耦合到每个单元的第一输入端以引入输入电压。 参考电压装置耦合到每个单元的第二输入端子以引入参考电压的渐进分数。 低阻抗装置耦合在相应的第一输出端子之间，并连接在连续的电池中的相应的第二输出端子之间，以将负载电流牵引到连续的电池，影响相对电压，从而减少电池错配对这些输出端子的影响。 最后，高阻抗装置耦合到连续单元中的每个第一输出端和每个第二输出端。

公开(公告)号：US06639430B2

公开(公告)日：2003-10-28

申请号：US10083463

申请日：2002-02-27

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G11C706

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

公开(公告)号：US6014098A

公开(公告)日：2000-01-11

申请号：US932163

申请日：1997-09-17

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M1/06 ,  H03M1/36 ,  H03M1/14

CPC classification number: H03M1/0646 ,  H03M1/36 ,  H03M1/365

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends. Different fractions of the reference voltage are associated with each individual impedance in the first and second sets. Such reference voltage fractions have a particular repetitive relationship. In this way, the number of output terminals is reduced and cell mismatches are reduced. The different outputs at each individual impedance are determined for the progressive fractions of the reference voltage at such impedance. Successive voltage fractions for each impedance have opposite polarities to provide a folding relationship. Such outputs may be cascaded to further reduce cell mismatches and the number of output terminals.

公开(公告)号：US5285171A

公开(公告)日：1994-02-08

申请号：US922300

申请日：1992-07-30

Applicant: Klaas Bult ,  Godefridus J. G. M. Geelen

Inventor： Klaas Bult ,  Godefridus J. G. M. Geelen

IPC: H03F3/343 ,  H03F1/22 ,  H03F3/345 ,  H03F3/347 ,  H03K3/16

CPC classification number: H03F1/223

Abstract: An amplifier arrangement comprises a first transistor (N1) having a control electrode coupled to an input terminal for receiving an input signal (Vin), a first main electrode coupled to a first supply-voltage terminal (2), and having a second main electrode. A second transistor (N2) has a control electrode, a first main electrode coupled to the second main electrode of the first transistor, and a second main electrode coupled to a second supply-voltage terminal (3) by means of a current source (J1). An output terminal supplies an output signal (Vout). An amplifier (N4, N5) has an inverting input (V1) coupled to the second main electrode of the first transistor, and an output (V0) coupled to the control electrode of the second transistor. An apparatus (N3, N6, N7, N8, P1, P2, P3, P4) is provided for correcting a first potential on the second main electrode of the first transistor depending upon a second potential on the control electrode of the first transistor in a manner such that the first transistor is operated at a desired point of saturation.

Abstract translation: 放大器装置包括：第一晶体管（N1），其具有耦合到用于接收输入信号（Vin）的输入端子的控制电极;耦合到第一电源电压端子（2）的第一主电极，并且具有第二主电极 。 第二晶体管（N2）具有控制电极，耦合到第一晶体管的第二主电极的第一主电极和借助于电流源（J1）耦合到第二电源电压端子（3）的第二主电极 ）。 输出端子提供输出信号（Vout）。 放大器（N4，N5）具有耦合到第一晶体管的第二主电极的反相输入端（V1）和耦合到第二晶体管的控制电极的输出端（V0）。 提供了一种装置（N3，N6，N7，N8，P1，P2，P3，P4），用于根据第一晶体管的控制电极上的第二电位来校正第一晶体管的第二电位上的第一电位 使得第一晶体管在期望的饱和点处工作。

公开(公告)号：US07848724B2

公开(公告)日：2010-12-07

申请号：US11432435

申请日：2006-05-12

Applicant: Klaas Bult ,  Rudy van de Plassche ,  Pieter Vorenkamp ,  Arnoldus Venes

Inventor： Klaas Bult ,  Rudy van de Plassche ,  Pieter Vorenkamp ,  Arnoldus Venes

IPC: H04B1/06 ,  H03F3/45

CPC classification number: H03G3/30 ,  H03F1/34 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45644 ,  H03G1/0029 ,  H04B2001/0433

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract translation: 综合通信系统。 包括具有设置在基板上的接收器的基板，用于将接收信号转换成IF信号。 耦合到VGA用于低电压应用并耦合到接收机处理IF信号。 VGA包括具有第一组差分晶体管组和第二组差分晶体管组的存储体对。 银行对并行交叉耦合，IF信号被施加到从用于在一定范围的输入电压上控制存储体对的跨导输出增益的控制信号去耦的存储体对。 数字IF解调器设置在衬底上并耦合到用于低电压应用的VGA，用于将IF信号转换成解调的基带信号。 并且发射机设置在与接收器协作操作的基板上以建立双向通信路径。

公开(公告)号：US07605734B2

公开(公告)日：2009-10-20

申请号：US11980393

申请日：2007-10-31

Applicant: Klaas Bult ,  Chi-Hung Lin

Inventor： Klaas Bult ,  Chi-Hung Lin

IPC: H03M1/66

CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

公开(公告)号：US07515895B2

公开(公告)日：2009-04-07

申请号：US11050107

申请日：2005-02-04

Applicant: Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr

Inventor： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr

IPC: H04B1/10

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。