公开(公告)号：US20080277759A1

公开(公告)日：2008-11-13

申请号：US12174020

申请日：2008-07-16

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L29/00

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

Abstract translation: 半导体结构。 半导体结构包括：在衬底内具有金属布线层的衬底; 在所述基板的顶表面上和上方的覆盖层; 在覆盖层的顶表面上和上方的绝缘层; 电感器，包括绝缘层中和上方的第一部分和仅在绝缘层上方的第二部分; 以及所述绝缘层内的引线接合焊盘，其中所述电感器的第一部分在第一方向上的高度大于所述引线接合焊盘在所述第一方向上的高度，其中所述第一方向垂直于所述基板的顶表面 朝向绝缘层。

公开(公告)号：US20080272458A1

公开(公告)日：2008-11-06

申请号：US12174047

申请日：2008-07-16

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L29/00

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

Abstract translation: 半导体结构。 半导体结构包括：在衬底内具有金属布线层的衬底; 衬底上方的覆盖层; 覆盖层上方的绝缘层; 绝缘层上方的第一层可光成像材料; 第一层可光成像材料上方的氧化层; 位于氧化层上方的第二层可光成像材料; 电感; 和引线键合垫。 电感器的第一部分在第二层可光成像材料中，氧化层，第一层可光成像材料，绝缘层和封盖层。 电感器的第二部分仅在第二层可光成像材料中。 导线焊盘仅在第一层可光成像材料，绝缘层和封盖层中。

公开(公告)号：US20080224259A1

公开(公告)日：2008-09-18

申请号：US12106374

申请日：2008-04-21

Applicant: Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L29/00 ,  H01L21/02

CPC classification number: H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US20080185684A1

公开(公告)日：2008-08-07

申请号：US12098479

申请日：2008-04-07

Applicant: Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L29/92

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

公开(公告)号：US07394145B2

公开(公告)日：2008-07-01

申请号：US11928798

申请日：2007-10-30

Applicant: Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract translation: 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20080054393A1

公开(公告)日：2008-03-06

申请号：US11928798

申请日：2007-10-30

Applicant: Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

Inventor： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

IPC: H01L29/00 ,  H01L21/02

CPC classification number: H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract translation: 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20070152332A1

公开(公告)日：2007-07-05

申请号：US11306596

申请日：2006-01-04

Applicant: Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

Inventor： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

IPC: H01L21/44

CPC classification number: H01L21/76838 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.

Abstract translation: 本发明涉及包括通孔级布线和/或器件的集成电路。 具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。 第一和第二线路级均包括金属布线和/或电子设备。 通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。 此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

公开(公告)号：US20060270247A1

公开(公告)日：2006-11-30

申请号：US10908789

申请日：2005-05-26

Applicant: Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

Inventor： Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

IPC: H01L21/336

CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28194 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

Abstract translation: 公开了形成高介电常数电介质层的方法，包括提供包括用于支撑衬底的保持器的处理室，引入包含高介电常数（Hi-K）电介质前体和氧（O 2） / SUB>）氧化剂进入处理室以形成衬底上的高介电常数电介质层的第一部分，并且从第一气体的流动切换到包括Hi-K电介质前体的第二气体的流动，以及 臭氧（O 3 3）氧化剂以形成第一部分上的高介电常数介电层的第二部分。 在替代实施例中，可以使用氧氧化剂在第二部分上形成另一部分。 本发明将产量提高了至少20％，而没有可靠性或泄漏降级，并且不需要额外的设备。

公开(公告)号：US07005371B2

公开(公告)日：2006-02-28

申请号：US10709357

申请日：2004-04-29

Applicant: Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

Inventor： Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

IPC: H01L21/4763

CPC classification number: H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract translation: 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。