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    Methods for fabricating SOI devices
    43.
    发明授权
    Methods for fabricating SOI devices 有权
    制造SOI器件的方法

    公开(公告)号：US07803674B2

    公开(公告)日：2010-09-28

    申请号：US12468131

    申请日：2009-05-19

    Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

    Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

    IPC: H01L21/84

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

    Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

    Abstract translation: 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

    APPARATUS, SYSTEM, AND METHOD FOR COOPERATION BETWEEN A BROWSER AND A SERVER TO PACKAGE SMALL OBJECTS IN ONE OR MORE ARCHIVES
    44.
    发明申请
    APPARATUS, SYSTEM, AND METHOD FOR COOPERATION BETWEEN A BROWSER AND A SERVER TO PACKAGE SMALL OBJECTS IN ONE OR MORE ARCHIVES 审中-公开
    浏览器和服务器之间的合作的装置，系统和方法，用于在一个或多个存档中包装小对象

    公开(公告)号：US20090063622A1

    公开(公告)日：2009-03-05

    申请号：US11847299

    申请日：2007-08-29

    Applicant: Long Cheng ,  Catherine C. Diep ,  Dong Jun Lan ,  Sheng S. Lu ,  Luis J. Ostdiek ,  Qing Bo Wang ,  Meng Ye

    Inventor： Long Cheng ,  Catherine C. Diep ,  Dong Jun Lan ,  Sheng S. Lu ,  Luis J. Ostdiek ,  Qing Bo Wang ,  Meng Ye

    IPC: G06F15/16

    CPC classification number: H04L67/02 ,  G06F16/957 ,  H04L69/04

    Abstract: An apparatus, system, and method are disclosed for reducing the loading time of a web page. In one embodiment, the apparatus, system, and method comprise requesting a web page from a web server, wherein requesting a web page from a web server comprises sending a browser parameter comprising an indicator to the web server, the indicator indicating that a browser is capable of receiving an archive. The present invention may further comprise receiving one or more archives from the web server, the one or more archives each comprising a plurality of archivable objects referenced by the web page, and rendering the web page using the plurality of archivable objects from the one or more archives.

    Abstract translation: 公开了一种用于减少网页的加载时间的装置，系统和方法。 在一个实施例中，装置，系统和方法包括从Web服务器请求网页，其中从网络服务器请求网页包括将包括指示符的浏览器参数发送到web服务器，该指示符指示浏览器是 能够接收档案。 本发明还可以包括从网络服务器接收一个或多个档案，所述一个或多个存档，每个存档包括网页引用的多个可归档对象，以及使用来自所述一个或多个的多个可存档对象来渲染网页 档案。

    ORGANIC THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME
    45.
    发明申请
    ORGANIC THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME 审中-公开
    有机薄膜晶体管阵列和包括其的液晶显示器

    公开(公告)号：US20090053851A1

    公开(公告)日：2009-02-26

    申请号：US12262009

    申请日：2008-10-30

    Applicant: Yih-Jun Wong ,  Horng-Long Cheng ,  Yu-Wu Wang

    Inventor： Yih-Jun Wong ,  Horng-Long Cheng ,  Yu-Wu Wang

    IPC: H01L51/40 ,  G02F1/136

    CPC classification number: G02F1/133553 ,  G02F1/136227

    Abstract: An organic thin film transistor array substrate including a substrate divided into an LCD region and an OTFT region; a first dielectric layer formed on the substrate in the LCD region and having a first uneven portion; an organic semiconducting layer formed on the substrate in the OTFT region; a gate, source, and drain formed in the OTFT region, wherein the source and drain are in contact with the organic semiconducting layer to form a channel between the source and drain; and a pixel electrode formed on the first uneven portion of the first dielectric layer in the LCD region.

    Abstract translation: 一种有机薄膜晶体管阵列基板，包括分为LCD区域和OTFT区域的基板; 形成在所述LCD区域的所述基板上并具有第一凹凸部的第一电介质层; 形成在OTFT区域的基板上的有机半导体层; 在OTFT区域中形成的栅极，源极和漏极，其中源极和漏极与有机半导体层接触以在源极和漏极之间形成沟道; 以及形成在LCD区域中的第一电介质层的第一凹凸部上的像素电极。

    IMAGE DATA COMPRESSION METHOD AND APPARATUSES, IMAGE DISPLAY METHOD AND APPARATUSES
    46.
    发明申请
    IMAGE DATA COMPRESSION METHOD AND APPARATUSES, IMAGE DISPLAY METHOD AND APPARATUSES 失效
    图像数据压缩方法和装置，图像显示方法和装置

    公开(公告)号：US20080080778A1

    公开(公告)日：2008-04-03

    申请号：US11861770

    申请日：2007-09-26

    Applicant: Long Cheng ,  Yi Fang ,  Qi Liang ,  Pu Yang ,  Yi Xu ,  Zhe Mo

    Inventor： Long Cheng ,  Yi Fang ,  Qi Liang ,  Pu Yang ,  Yi Xu ,  Zhe Mo

    IPC: G06K9/36 ,  G06T1/20

    CPC classification number: H04N19/176 ,  H04N19/436 ,  H04N19/46

    Abstract: The image data compression method involves the performing of steps: a block dividing step for dividing a computer processor pipeline statistic image to be displayed into a plurality of blocks with predetermined block width and block height; a block list creating step for creating a block list for indexed blocks containing meaningful pixels in said divided blocks such that said indexed blocks are associated with each other, wherein said meaningful pixels are pixels corresponding to the computer processor pipeline raw trace data; and a pixel information compressing step for compressing original pixel information on the meaningful pixels in said indexed blocks and storing it in said block list. Apparatus for performing the method is also provided.

    Abstract translation: 图像数据压缩方法包括执行步骤：块分割步骤，用于将要显示的计算机处理器流水线统计图像划分成具有预定块宽度和块高度的多个块; 块列表创建步骤，用于在所述分割块中创建包含有意义像素的索引块的块列表，使得所述索引块相互关联，其中所述有意义的像素是与计算机处理器管线原始跟踪数据相对应的像素; 以及像素信息压缩步骤，用于压缩所述索引块中有意义的像素上的原始像素信息并将其存储在所述块列表中。 还提供了用于执行该方法的装置。

    Selective formation of stress memorization layer
    47.
    发明申请
    Selective formation of stress memorization layer 失效
    选择性形成应力记忆层

    公开(公告)号：US20080003734A1

    公开(公告)日：2008-01-03

    申请号：US11520377

    申请日：2006-09-13

    Applicant: Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

    Inventor： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/7843

    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

    Abstract translation: 一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成 在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。 在具有NMOS器件的区域中，相同的应力记忆层没有减小。 在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

    SELF-ASSEMBLY OF MOLECULAR DEVICES
    48.
    发明申请
    SELF-ASSEMBLY OF MOLECULAR DEVICES 审中-公开
    分子装置自组装

    公开(公告)号：US20070297216A1

    公开(公告)日：2007-12-27

    申请号：US11740170

    申请日：2007-04-25

    Applicant: James Tour ,  Jiping Yang ,  Philipp Harder ,  David Allara ,  Paul Weiss ,  Long Cheng ,  Paul Franzon ,  David Nackashi

    Inventor： James Tour ,  Jiping Yang ,  Philipp Harder ,  David Allara ,  Paul Weiss ,  Long Cheng ,  Paul Franzon ,  David Nackashi

    IPC: G11C11/56 ,  B05D1/04 ,  C25D5/00 ,  H01L45/00 ,  H01L21/62 ,  C25D5/10

    CPC classification number: H01L51/0595 ,  B82Y10/00 ,  C25D9/00 ,  H01L51/005 ,  H01L51/0075

    Abstract: A method for selectively assembling a molecular device on a substrate comprises contacting the first substrate with a solution containing molecular devices; impeding bonding of the molecular devices to the substrate such that application of a voltage potential to the substrate results in assembly of the molecular device on the substrate at a rate that is at least 1.5 times the rate of assembly of the molecular device on a voltage-neutral substrate; and applying a voltage potential to the substrate so as to cause the molecular devices to assemble on the substrate. A nanoscale computing device is described that includes a substrate, a pair of conductive input/output electrodes carried on this substrate and disposed in spaced-apart relationship and a substantially disordered assembly of nanowires formed on the substrate in a region between the electrodes, thereby forming at least one programmable conductive pathway between the pair of electrodes.

    Abstract translation: 用于在基片上选择性地组装分子器件的方法包括使第一底物与含有分子器件的溶液接触; 妨碍分子器件与衬底的结合，使得向衬底施加电压电位导致分子器件在衬底上的组装速度至少是分子器件在电压 - 电压上的组装速度的1.5倍， 中性底物; 以及向所述衬底施加电压电位以使所述分子器件组装在所述衬底上。 描述了一种纳米尺度计算装置，其包括衬底，一对导电输入/输出电极，该导电输入/输出电极承载在该衬底上并以间隔的关系设置，并且在电极之间的区域中形成在衬底上的基本上无序的纳米线组件，从而形成 在一对电极之间的至少一个可编程导电路径。

    Organic thin film transistor array substrate and liquid crystal display including the same
    49.
    发明授权
    Organic thin film transistor array substrate and liquid crystal display including the same 有权
    有机薄膜晶体管阵列基板和液晶显示器包括相同的

    公开(公告)号：US07253848B2

    公开(公告)日：2007-08-07

    申请号：US10458335

    申请日：2003-06-10

    Applicant: Yih-Jun Wong ,  Horng-Long Cheng ,  Yu-Wu Wang

    Inventor： Yih-Jun Wong ,  Horng-Long Cheng ,  Yu-Wu Wang

    IPC: G02F1/136

    CPC classification number: G02F1/133553 ,  G02F1/136227

    Abstract: An organic thin film transistor array substrate including a substrate divided into an LCD region and an OTFT region; a first dielectric layer formed on the substrate in the LCD region and having a first uneven portion; an organic semiconducting layer formed on the substrate in the OTFT region; a gate, source, and drain formed in the OTFT region, wherein the source and drain are in contact with the organic semiconducting layer to form a channel between the source and drain; and a pixel electrode formed on the first uneven portion of the first dielectric layer in the LCD region.

    Abstract translation: 一种有机薄膜晶体管阵列基板，包括分为LCD区域和OTFT区域的基板; 形成在所述LCD区域的所述基板上并具有第一凹凸部的第一电介质层; 形成在OTFT区域的基板上的有机半导体层; 在OTFT区域中形成的栅极，源极和漏极，其中源极和漏极与有机半导体层接触以在源极和漏极之间形成沟道; 以及形成在LCD区域中的第一电介质层的第一凹凸部上的像素电极。

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