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    REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
    42.
    发明申请
    REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD 有权
    SOI结构和方法中减少的角膜泄漏

    公开(公告)号：US20110291169A1

    公开(公告)日：2011-12-01

    申请号：US12791372

    申请日：2010-06-01

    申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L27/12 ,  H01L21/86 ,  H01L29/78

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

    摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

    摘要翻译： 通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案 在有源层中，用绝缘体代替导电沟道的去除部分。 传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积 通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

    DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
    43.
    发明申请
    DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
    在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器

    公开(公告)号：US20110092043A1

    公开(公告)日：2011-04-21

    申请号：US12974451

    申请日：2010-12-21

    申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

    发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

    IPC分类号： H01L21/02

    CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

    摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

    摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

    CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD
    44.
    发明申请
    CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD 审中-公开
    内容可寻址存储器，具有隐藏表更新，设计结构和方法

    公开(公告)号：US20090240875A1

    公开(公告)日：2009-09-24

    申请号：US12050340

    申请日：2008-03-18

    申请人： Albert M. Chu ,  Paul C. Parries ,  Daryl M. Seitzer

    发明人： Albert M. Chu ,  Paul C. Parries ,  Daryl M. Seitzer

    IPC分类号： G11C15/04 ,  G11C7/00

    CPC分类号： G11C15/043 ,  G11C11/406

    摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.

    摘要翻译： 公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。 第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。 第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。 第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。 由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。 还公开了相关设计结构和方法的实施例。

    DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
    45.
    发明申请
    DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
    在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器

    公开(公告)号：US20090184356A1

    公开(公告)日：2009-07-23

    申请号：US12016312

    申请日：2008-01-18

    申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

    发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

    IPC分类号： H01L29/94 ,  H01L21/20

    CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

    摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

    摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

    DRAM HAVING DEEP TRENCH CAPACITORS WITH LIGHTLY DOPED BURIED PLATES
    46.
    发明申请
    DRAM HAVING DEEP TRENCH CAPACITORS WITH LIGHTLY DOPED BURIED PLATES 有权
    具有轻型镀锌板的深层电容电容器的DRAM

    公开(公告)号：US20090174031A1

    公开(公告)日：2009-07-09

    申请号：US11969986

    申请日：2008-01-07

    申请人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

    发明人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

    IPC分类号： H01L29/92 ,  H01L21/28 ,  G06F17/50

    CPC分类号： H01L29/66181 ,  G11C11/404 ,  H01L27/0805 ,  H01L27/10861

    摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

    摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。

    PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR
    47.
    发明申请
    PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR 有权
    提供隔离通过深度电容电容器进行字线传输

    公开(公告)号：US20090173980A1

    公开(公告)日：2009-07-09

    申请号：US11969989

    申请日：2008-01-07

    申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Herbert L. Ho ,  Paul C. Parries

    发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Herbert L. Ho ,  Paul C. Parries

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1087 ,  H01L27/10891

    摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.

    摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

    Low power manager for standby operation of a memory system
    49.
    发明授权
    Low power manager for standby operation of a memory system 有权
    低功耗管理器用于存储系统的待机操作

    公开(公告)号：US07023758B2

    公开(公告)日：2006-04-04

    申请号：US11205565

    申请日：2005-08-17

    申请人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    发明人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    IPC分类号： G11C7/00

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

    摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

    Concurrent refresh mode with distributed row address counters in an embedded DRAM
    50.
    发明授权
    Concurrent refresh mode with distributed row address counters in an embedded DRAM 有权
    并行刷新模式，在嵌入式DRAM中具有分布式行地址计数器

    公开(公告)号：US06967885B2

    公开(公告)日：2005-11-22

    申请号：US10757846

    申请日：2004-01-15

    申请人： John E. Barth, Jr. ,  Toshiaki Kirihata ,  Paul C. Parries

    发明人： John E. Barth, Jr. ,  Toshiaki Kirihata ,  Paul C. Parries

    IPC分类号： G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

    摘要： A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

    摘要翻译： 通过允许通过刷新存储体选择信号刷新存储器阵列，同时使能另一阵列中的存储器访问操作来实现并发刷新模式。 通过插入集成在每个阵列中的行地址计数器，可以大大简化刷新地址管理。 在优选实施例中，同时刷新多个存储器阵列的任何组合，同时实现存储器访问操作。 此并发模式还支持多银行操作。