公开(公告)号：US20140375386A1

公开(公告)日：2014-12-25

申请号：US14343894

申请日：2012-10-08

Applicant: ST-Ericsson SA

Inventor： Frederic Rivoirard

IPC: H03F1/32 ,  H03F3/21 ,  H03F3/45 ,  H03F3/193

CPC classification number: H03F1/3205 ,  H03F1/26 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/45273 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45091 ,  H03F2203/45306 ,  H03F2203/45311 ,  H03F2203/45312 ,  H03F2203/45334 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45562 ,  H03F2203/45576

Abstract: The low-noise amplifier circuit exhibits reduced noise.

Abstract translation: 低噪声放大器电路表现出降低的噪声。

公开(公告)号：US20140347128A1

公开(公告)日：2014-11-27

申请号：US14358182

申请日：2012-10-30

Applicant: ST-Ericsson SA

Inventor： Carlo Crippa ,  Rossella Bassoli

IPC: H03F3/185 ,  H03F3/217 ,  H03K7/08

CPC classification number: H03F3/185 ,  H03F3/187 ,  H03F3/2175 ,  H03F3/45475 ,  H03F2200/165 ,  H03F2200/351 ,  H03F2200/78 ,  H03F2203/21112 ,  H03F2203/21196 ,  H03K7/08

Abstract: A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]).

Abstract translation: 公开了一种数字D类放大器（10），包括：脉冲宽度调制器（PW Mod），包括：适于接收输入信号（x [n]）和反馈信号（fb [n]）的数字环路滤波器 ]），所述数字环路滤波器（Loop_F）适于以时钟频率（f_s）处理所述输入和反馈信号，以提供经过滤波的数字信号（w [n]）作为输出; PWM转换模块（PW_CM），其具有用于接收经过滤波的数字信号（w [n]）并具有连接到数字环路滤波器（Loop F）的第一输出端25的输入端） 用于处理滤波后的数字信号（w [n]）并在所述第一输出端提供反馈信号（fb [n]）。 PWM转换模块（PW_CM）包括：第一比较器（CMP_N），适于将滤波后的数字信号（w [n]）与第一参考三角波形（VTn [n]）进行比较，以提供第一PWM信号 [n]），具有比所述时钟频率（fs）低得多的频率（f_osc）的第一参考三角波形; 适于将滤波后的数字信号（w [n]）与第二参考三角波形（VTp [n]）进行比较以用于提供第二PWM信号（yp [n]）作为输出的第二比较器（CMP_P），第二参考三角形 波形（VTp [n]）是第一三角波形（VTn [n]）的倒数，所述第一（yn [n]）和第二（yp [n]）PWM信号表示差分输出脉宽调制信号 [n]，yp [n]）。

公开(公告)号：US08890735B2

公开(公告)日：2014-11-18

申请号：US14351059

申请日：2012-10-08

Applicant: ST-Ericsson SA

Inventor： Carlo Pinna

IPC: H03M3/00

CPC classification number: H03M3/422 ,  H03M3/39 ,  H03M3/424 ,  H03M3/454

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径，其包括计算块，模拟积分器和具有降低量化级别的量化器。 此外，转换器包括反馈路径，其被布置为向计算块提供反馈模拟信号。 直接路径包括具有与反馈路径的第二放大块的增益因子相反的增益因子的第一放大块。 该转换器允许降低量化器的复杂性。

公开(公告)号：US20140334632A1

公开(公告)日：2014-11-13

申请号：US14301115

申请日：2014-06-10

Applicant: ST-ERICSSON INDIA PVT. LTD. ,  ST-ERICSSON SA

Inventor： SANJEEV RANGANATHAN ,  SHYAM SOMAYAJULA ,  SRINATH SRIDHARAN ,  LIONEL CIMAZ

IPC: H04R3/00 ,  G10K11/00

CPC classification number: H04R3/002 ,  G10K11/002 ,  H04R3/00 ,  H04R3/007

Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.

Abstract translation: 公开了用于抑制音频信号中的弹出噪声的系统和方法。 该系统包括由引脚接口和互补引脚接口共享的驱动器电路。 控制单元耦合到引脚接口和互补引脚接口。 要激活引脚接口，控制单元配置为首先在互补引脚接口处激活驱动器输出。 一旦互补引脚接口达到预设电压，驱动器输出就由控制单元切换到引脚接口。 此外，可以通过重新使用在引脚接口处计算出的校准数据，在互补引脚接口上校准驱动器电路的直流偏移。 此外，可以基于驱动器电路的校准数据从预偏置电路提供直流校正信号。

公开(公告)号：US20140327745A1

公开(公告)日：2014-11-06

申请号：US14356698

申请日：2012-10-23

Applicant: ST-Ericsson SA

Inventor： Antoine Drouot

IPC: H04N5/225 ,  H04N13/02

CPC classification number: H04N5/2259 ,  G06T3/4038 ,  H04N9/76 ,  H04N13/204 ,  H04N13/221

Abstract: The invention concerns a method of generating at least a first panoramic picture and a second panoramic picture based on a series of frames acquired by one frame acquisition device while said device is panned in a main direction, a global motion value and a perspective transform being computed for each pair of consecutive frames of the series, the global motion value reflecting a displacement in the main direction between the frames of a pair of frames and the perspective transform reflecting a perspective change between the frames of a pair of frames. For each frame of the series, a first area of the frame is determined for the first panoramic picture and a second area of the frame, distinct from the first area, is determined for the second panoramic picture. The method comprises, upon acquisition of a current frame of the series of frames, determining a first frame among the already acquired frames of the series of frames, which has second area that shares at least a common area with the first area of the current frame, calculating a global transform based on the perspective transforms of the pairs of consecutive frames that have been acquired between the first frame and the current frame and determining an adapted first area by applying an inverse of the global transform to the first area of the current frame, the adapted first area being included into the first panoramic picture and the second area of the current frame being included into the second panoramic picture.

Abstract translation: 本发明涉及一种产生至少第一全景图像和第二全景图像的方法，该方法基于在一个主要方向上平移所述装置的同时由一个帧采集装置获取的一系列帧，计算全局运动值和透视变换 对于该系列的每对连续帧，反映一对帧的帧之间的主方向上的位移的全局运动值和反映一对帧的帧之间的透视变化的透视变换。 对于该系列的每个帧，为第一全景图像确定帧的第一区域，并且为第二全景图片确定与第一区域不同的帧的第二区域。 所述方法包括：在获取所述一系列帧的当前帧时，确定所述一系列帧的已经获取的帧中的第一帧，其具有与当前帧的第一区域共享至少公共区域的第二区域 基于在第一帧和当前帧之间获取的连续帧对的透视变换来计算全局变换，并且通过将全局变换的逆向应用于当前帧的第一区域来确定适配的第一区域 被适配的第一区域被包括在第一全景图像中，并且当前帧的第二区域被包括在第二全景图像中。

公开(公告)号：US08879611B2

公开(公告)日：2014-11-04

申请号：US13629993

申请日：2012-09-28

Applicant: ST-Ericsson SA

Inventor： Achraf Dhayni ,  Jeroen Kuenen

IPC: H04B17/00

CPC classification number: H04B17/004 ,  H04B17/0085 ,  H04B17/20 ,  H04B17/29

Abstract: A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

Abstract translation: 内置的接收机自检系统提供片上测试，对接收机的占位面积进行最小的改变。 该系统数字地产生双音测试信号，并使用生成的双音测试信号测试接收机的非线性。 为此，自检系统包括一个刺激发生器，一个下变频器和一个解调器，所有这些都设置在公共的接收芯片上。 刺激发生器产生测试信号，该测试信号包括相应的第一和第二频率处的第一和第二音调，其中第一和第二频率间隔偏移频率，并且其中第一频率包括偏移频率的非整数倍。 下变频器将测试信号下变频以产生同相分量和正交分量。 解调器通过基于参考频率解调同相和正交分量来测量互调音的幅度。

公开(公告)号：US20140301279A1

公开(公告)日：2014-10-09

申请号：US13856554

申请日：2013-04-04

Applicant: ST-ERICSSON SA

Inventor： Fabrice CHERUEL

IPC: H04W72/08 ,  H04W24/02

CPC classification number: H04W24/02 ,  H04L5/0073 ,  H04W72/00

Abstract: Methods and systems for performing interference mitigation (immunity management) in a radio communication device. A list of frequencies is provided from at least one radio subsystem to an immunity management (IMM) module. The IMM module determines whether any of the frequencies in the list represent a conflict with harmonics associated with one or more clock frequencies associated with one or more embedded systems. If a conflict exists, then the IMM module makes a change in the fundamental frequency of the corresponding clock to remove the conflict, while also ensuring that other frequencies in the list are not impacted by the change. The potential need to change clock frequencies can be evaluated at state transitions of the device, e.g., call establishment, call release, handover or channel re-allocation events.

Abstract translation: 用于在无线电通信设备中执行干扰减轻（抗扰度管理）的方法和系统。 从至少一个无线电子系统到免疫管理（IMM）模块提供频率列表。 IMM模块确定列表中的任何频率是否表示与与一个或多个嵌入式系统相关联的一个或多个时钟频率相关联的谐波的冲突。 如果存在冲突，则IMM模块会改变相应时钟的基频以消除冲突，同时还要确保列表中的其他频率不受更改的影响。 可以在设备的状态转换（例如呼叫建立，呼叫释放，切换或信道重新分配事件）处评估改变时钟频率的潜在需要。

公开(公告)号：US20140300335A1

公开(公告)日：2014-10-09

申请号：US14353991

申请日：2012-09-25

Applicant: ST-Ericsson SA

Inventor： Benoit Labbe ,  David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M3/156

Abstract: A circuit with current-controlled frequency implements a node (2) with an electrical charge which alternatively increases and decreases between two thresholds. The slew rate of the node can be adjusted using a tunable current source (1), thereby enabling tuning of a switching delay. The circuit may be used for controlling the switching frequency of a switch-mode power supply.

Abstract translation: 具有电流控制频率的电路实现具有在两个阈值之间可选地增加和减少的电荷的节点（2）。 可以使用可调电流源（1）来调整节点的转换速率，从而实现对开关延迟的调节。 该电路可用于控制开关模式电源的开关频率。

公开(公告)号：US20140258765A1

公开(公告)日：2014-09-11

申请号：US13784909

申请日：2013-03-05

Applicant: ST-ERICSSON SA

Inventor： Håkan Persson

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Abstract translation: 通过将具有不同相对相位的时钟信号施加到CPU的不同部分，由于CPU内部的逻辑切换引起的高频电流瞬变被减少。 这降低了电流变化的幅度，并因此降低了对电源电压的感应。 在一些实施例中，多核CPU内的不同CPU内核以不同的时钟相位计时。 另外，提供了在存在大的OCV效应的情况下用于低等待时间通信的方法和电路。 低延迟通信可以基于FIFO。 标记用于指示安全点在更新和读取发射机和接收机之间的信号。 选通在中央时钟发生模块中产生。 选通机制用于在发送器和接收器之间传送读取和写入指针，同时使用允许数据写入与相应数据读取异步的FIFO数据数据传输有效载荷数据。

公开(公告)号：US20140256274A1

公开(公告)日：2014-09-11

申请号：US14353655

申请日：2012-10-17

Applicant: ST-Ericsson SA

Inventor： Vincent Knopik

IPC: H04B1/44

CPC classification number: H04B1/44 ,  H04B1/0458 ,  H04B1/406

Abstract: There is described a RF front end circuit comprising: a common impedance matching network (4) connected to an output terminal (5), a first power amplifier (1), PA, arranged to drive power to the output terminal through the common impedance matching network, a second PA (2) adapted to drive power to the output terminal through the common impedance matching network and a second impedance matching network (12), a reference terminal (9, 92) at a reference voltage (Vdd2), the second impedance matching network comprising at least a first connection path to the reference terminal, a second connection path to the second PA and a third connection path to the common impedance matching network, wherein, the second impedance matching network comprises a first impedance switch (SI1) configured to open the first connection path responsive to the second PA being put into an OFF state.

Abstract translation: 描述了一种RF前端电路，包括：连接到输出端子（5）的公共阻抗匹配网络（4），第一功率放大器（1），PA，布置成通过公共阻抗匹配来向输出端子驱动电力 网络，适于通过公共阻抗匹配网络向第二输出端子驱动电力的第二PA（2）和第二阻抗匹配网络（12），参考电压（Vdd2）的参考端子（9,92），第二阻抗匹配网络 阻抗匹配网络，包括至少到参考终端的第一连接路径，到第二PA的第二连接路径和到公共阻抗匹配网络的第三连接路径，其中，第二阻抗匹配网络包括第一阻抗开关（SI1） 被配置为响应于所述第二PA被置于OFF状态来打开所述第一连接路径。