公开(公告)号：US12119746B2

公开(公告)日：2024-10-15

申请号：US17807466

申请日：2022-06-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Borghese ,  Mattia Carrera

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/0016 ,  H02M1/0022 ,  H02M1/0025

Abstract: In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.

公开(公告)号：US12117942B2

公开(公告)日：2024-10-15

申请号：US18109675

申请日：2023-02-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics SA

Inventor： Roberta Vittimani ,  Federico Goller ,  Riccardo Angrilli ,  Charles Aubenas

IPC: G06F12/14

CPC classification number: G06F12/1441 ,  G06F12/1458

Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

公开(公告)号：US12113103B2

公开(公告)日：2024-10-08

申请号：US18062524

申请日：2022-12-06

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Antonello Santangelo ,  Giuseppe Longo ,  Lucio Renna

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.

公开(公告)号：US12106201B2

公开(公告)日：2024-10-01

申请号：US17039653

申请日：2020-09-30

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Carmine Cappetta ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/04 ,  G06F9/38 ,  G06F13/16 ,  G06F13/40 ,  G06N3/063 ,  G06T7/11

CPC classification number: G06N3/04 ,  G06F9/3806 ,  G06F13/1657 ,  G06F13/1673 ,  G06F13/4022 ,  G06N3/063 ,  G06T7/11 ,  G06T2207/20084

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

公开(公告)号：US12101104B2

公开(公告)日：2024-09-24

申请号：US17721110

申请日：2022-04-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto Modaffari ,  Paolo Pesenti

IPC: H03M3/00

CPC classification number: H03M3/384 ,  H03M3/422 ,  H03M3/436 ,  H03M3/464 ,  H03M3/496

Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

公开(公告)号：US12085393B2

公开(公告)日：2024-09-10

申请号：US17198160

申请日：2021-03-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Enrico Rosario Alessi ,  Fabio Passaniti

IPC: G01C21/20 ,  A61B5/00 ,  A61B5/11 ,  G01C5/06

CPC classification number: G01C21/206 ,  A61B5/1118 ,  A61B5/681 ,  G01C5/06 ,  A61B2560/0209 ,  A61B2560/0257 ,  A61B2562/0219

Abstract: A user context and/or activity detection device envisages a pressure sensor, configured to provide a pressure signal; an electrostatic-charge-variation sensor, configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the user; and a processing unit, which is coupled to the pressure sensor and to the electrostatic-charge-variation sensor so as to receive the pressure signal and the charge-variation signal and is configured to jointly process the pressure signal and charge-variation signal for detecting changes in level or altitude.

公开(公告)号：US12080631B2

公开(公告)日：2024-09-03

申请号：US17463140

申请日：2021-08-31

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Luca Grandi

IPC: H01L23/485 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/485 ,  H01L21/561 ,  H01L23/3107

Abstract: The present disclosure is directed to a semiconductor package including a first laser direct structuring (LDS) resin layer and a second LDS resin layer on the first LDS resin layer. Respective surfaces of the first LDS resin layer and the second LDS resin layer are patterned utilizing an LDS process by exposing the respective surfaces to a laser. Patterning the first and second LDS resin layers, respectively, activates additive material present within the first and second LDS resin layers, respectively, converting the additive material from a non-conductive state to a conductive state. The LDS process is followed by a chemical plating step and an electrolytic plating process to form conductive structure coupled to a plurality of die within the first and second LDS resin layers. A molding compound layer is formed on surfaces of the conductive structures and covers the surfaces of the conductive structures. After these steps have been completed, the first LDS resin layer and the second LDS resin layer are singulated along channels filled with conductive material.

公开(公告)号：US20240291387A1

公开(公告)日：2024-08-29

申请号：US18437919

申请日：2024-02-09

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Stefano PERROTTA ,  Salvatore Giuseppe PRIVITERA ,  Francesco PULVIRENTI

IPC: H02M3/335 ,  H02M1/00 ,  H02M3/00 ,  H02M3/338

CPC classification number: H02M3/33523 ,  H02M1/0054 ,  H02M3/01 ,  H02M3/3384

Abstract: Provided is a DC-DC converter with galvanic isolation comprising a resonant oscillator coupled to a primary winding of a galvanic isolation transformer. A rectifier is coupled to a secondary winding of the transformer to provide an output voltage. The DC-DC converter comprises a regulation loop configured to regulate an output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator as a function of a result of a signal indicative of the comparison between the output voltage and the reference voltage. The resonant oscillator is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular sub-harmonic frequency, below a resonance frequency of the resonant oscillator which maximizes a quality factor of the resonant oscillator, in particular below a resonance frequency of a LC tank circuit comprised in the resonant oscillator which maximizes a quality factor of the LC tank circuit.

公开(公告)号：US12075236B2

公开(公告)日：2024-08-27

申请号：US17655867

申请日：2022-03-22

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Caserta ,  Amedeo Veneroso

IPC: H04W12/03 ,  H04W8/18 ,  H04W12/041 ,  H04W12/0431

CPC classification number: H04W12/03 ,  H04W8/18 ,  H04W12/041 ,  H04W12/0431

Abstract: A method for concealing a subscription identifier at a user equipment including a mobile equipment and an integrated circuit card storing the subscription identifier, the method including receiving a corresponding request by a server to provide a corresponding subscription identifier, performing an elliptical curve encryption of the subscription identifier generating a concealed subscription identifier, the concealing operation including the mobile equipment sending an identity retrieve command to the card, performing, before receiving the identity retrieve command at the card, a pre-calculation of the ephemeral key pair including an ephemeral private key and ephemeral public key and the shared secret key, and in response to the respective state of completion indicating that completion of the computation of a valid ephemeral key pair or shared secret key, storing the corresponding values of the ephemeral key pair and shared secret key in a table in a memory of the card.

公开(公告)号：US12073860B2

公开(公告)日：2024-08-27

申请号：US18191639

申请日：2023-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Dario Livornesi ,  Alessio Emanuele Vergani ,  Paolo Pulici ,  Francesco Piscitelli ,  Enrico Mammei ,  Mojtaba Mohammadi Abdevand ,  Piero Malcovati ,  Edoardo Bonizzoni

IPC: G11B5/60 ,  H03F1/02

CPC classification number: G11B5/6029 ,  G11B5/607 ,  H03F1/0261

Abstract: According to an embodiment, a circuit includes a biasing and a low-frequency recovery circuit. The biasing circuit includes a voltage digital to analog converter (V-DAC), a differential difference amplifier coupled to the V-DAC, a common-mode feedback (CMFB) amplifier coupled to the differential difference amplifier, and a first pair of transistors arranged as a high-impedance structure and coupled to the differential difference amplifier and the CMFB amplifier. The low-frequency recovery circuit includes a current digital to analog converter (C-DAC), a second pair of transistors arranged as a high-impedance structure and coupled to the first pair of transistors, a pair of resistors having a resistance value equal to half a resistance of the resistive sensor, the pair of resistors arranged between the second pair of transistors and coupled to the C-DAC, and a gain circuit coupled to shared nodes between the second pair of transistors and the pair of resistors.