公开(公告)号：US07331844B2

公开(公告)日：2008-02-19

申请号：US11406459

申请日：2006-04-19

Applicant: Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

Inventor： Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

IPC: B24B1/00

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A slurry feeding apparatus includes closed slurry bottle, piping, wet nitrogen generator, wet nitrogen supply pipe, suction and spray nozzles, temperature regulator, flow rate control valves, slurry delivery pump and controller for controlling the operation and flow rate of the slurry delivery pump. While a wafer is being polished by a CMP polisher, the controller continuously operates the pump. On the other hand, while the polisher is idling, the controller starts and stops the pump intermittently at regular intervals. No stirrer like a propeller is inserted into the slurry bottle, but the slurry is stirred up by spraying the slurry through the spray nozzle.

Abstract translation: 浆料输送装置包括封闭的浆液瓶，管道，湿氮发生器，湿氮供给管，抽吸喷嘴，温度调节器，流量控制阀，浆料输送泵和控制器，用于控制浆料输送泵的操作和流速 。 当晶圆被CMP抛光机抛光时，控制器连续地操作泵。 另一方面，当抛光机空转时，控制器会间歇地间歇地启动和停止泵。 没有像螺旋桨那样的搅拌器被插入到浆料瓶中，但是通过喷雾喷雾浆料来搅拌浆料。

公开(公告)号：US07190045B2

公开(公告)日：2007-03-13

申请号：US10812880

申请日：2004-03-31

Applicant: Kyoko Egashira ,  Shin Hashimoto

Inventor： Kyoko Egashira ,  Shin Hashimoto

IPC: H01L29/00

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

公开(公告)号：US07166018B2

公开(公告)日：2007-01-23

申请号：US10737910

申请日：2003-12-18

Applicant: Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

Inventor： Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

IPC: B24B1/00

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A slurry feeding apparatus includes closed slurry bottle, piping, wet nitrogen generator, wet nitrogen supply pipe, suction and spray nozzles, temperature regulator, flow rate control valves, slurry delivery pump and controller for controlling the operation and flow rate of the slurry delivery pump. While a wafer is being polished by a CMP polisher, the controller continuously operates the pump. On the other hand, while the polisher is idling, the controller starts and stops the pump intermittently at regular intervals. No stirrer like a propeller is inserted into the slurry bottle, but the slurry is stirred up by spraying the slurry through the spray nozzle.

Abstract translation: 浆料输送装置包括封闭的浆液瓶，管道，湿氮发生器，湿氮供给管，抽吸喷嘴，温度调节器，流量控制阀，浆料输送泵和用于控制浆料输送泵的操作和流速的控制器 。 当晶圆被CMP抛光机抛光时，控制器连续地操作泵。 另一方面，当抛光机空转时，控制器会间歇地间歇地启动和停止泵。 没有像螺旋桨那样的搅拌器被插入到浆料瓶中，但是通过喷雾喷雾浆料来搅拌浆料。

公开(公告)号：US06562716B2

公开(公告)日：2003-05-13

申请号：US09726654

申请日：2000-12-01

Applicant: Shin Hashimoto ,  Kyoko Egashira

Inventor： Shin Hashimoto ,  Kyoko Egashira

IPC: H01L21336

CPC classification number: H01L28/24 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/665 ,  H01L29/66545

Abstract: After a cobalt film is deposited on a silicon-containing film formed on a semiconductor substrate, a first heat treatment at a relatively low temperature is performed with respect to the semiconductor substrate to cause a reaction between the cobalt film and the silicon layer and thereby form a Co2Si layer or CoSi layer in at least a surface portion of the silicon layer. Then, a silicon-containing film is deposited on the Co2Si layer or CoSi layer and a second heat treatment at a relatively high temperature is performed with respect to the semiconductor substrate to cause a reaction between the silicon-containing film and the Co2Si layer or CoSi layer and thereby form a CoSi2 layer in at least a surface portion of the silicon layer.

Abstract translation: 在形成在半导体衬底上的含硅膜上沉积钴膜后，相对于半导体衬底进行相对低温的第一次热处理，以引起钴膜与硅层之间的反应，从而形成 在所述硅层的至少表面部分中的Co 2 Si层或CoSi层。 然后，在Co 2 Si层或CoSi层上沉积含硅膜，相对于半导体衬底进行相对高温的第二次热处理，以使含硅膜和Co 2 Si层或CoSi 从而在硅层的至少表面部分中形成CoSi 2层。

公开(公告)号：US06180423B2

公开(公告)日：2001-01-30

申请号：US09108323

申请日：1998-07-01

Applicant: Shin Hashimoto ,  Yoshiharu Hidaka

Inventor： Shin Hashimoto ,  Yoshiharu Hidaka

IPC: B24B100

CPC classification number: B24B53/017 ,  B24B37/042 ,  H01L21/02024 ,  H01L21/30625

Abstract: It is arranged such that the least common multiple of two numbers m and n of which one is prime to the other, is made as large as possible where the number m is the rotational speed (rpm) of a platen with a polishing pad affixed thereto and the number n is the rotational speed (rpm) of a carrier with a wafer mounted thereon. As a result of such arrangement, it is not until the platen completes m revolutions that a point on the polishing pad that comes into contact with a fixed point on the wafer returns to the original contact point with the fixed point at the start of polishing, and the resulting trajectory is therefore spread uniformly over the polishing pad. Each point on the wafer is brought into contact with most surface regions of the polishing pad, therefore preventing the wafer from undergoing deterioration in planarity uniformity due to a particular point on the wafer, on one hand, frequently coming into contact with low polishing-rate regions in the polishing pad and due to the other points on the wafer, on the other hand, less frequently coming into contact with the regions.

Abstract translation: 它被布置为使得其中一个是另一个的两个数m和n的最小公倍数被制成尽可能大，其中数字m是固定有抛光垫的压板的转速（rpm） 数字n是安装有晶片的载体的转速（rpm）。 作为这种布置的结果，直到压板完成m转，即抛光垫上的与晶片上的固定点接触的点在抛光开始时返回到与固定点的原始接触点， 并且所得到的轨迹因此均匀地分布在抛光垫上。 晶片上的每个点与抛光垫的大多数表面区域接触，因此防止晶片由于晶片上的特定点而在平坦度均匀性方面的劣化，一方面经常与低抛光速率接触 另一方面，抛光垫中的区域和晶片上的其它点，较不频繁地与该区域接触。

公开(公告)号：US5892368A

公开(公告)日：1999-04-06

申请号：US744082

申请日：1996-11-04

Applicant: Yoshiro Nakata ,  Shin Hashimoto ,  Isao Miyanaga

Inventor： Yoshiro Nakata ,  Shin Hashimoto ,  Isao Miyanaga

IPC: G01R31/28 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01R31/2884 ,  G01R31/2849

Abstract: A 12.5-MHz signal is applied from outside a semiconductor integrated circuit (SIC) device to a signal input terminal of that SIC device. A frequency multiplying circuit is fed that 12.5-MHz signal from the input terminal, and delivers a reference signal whose frequency is a multiple of the frequency of the signal received (i.e., 100 MHz), to a semiconductor memory and to a self-test circuit. The self-test circuit provides a test signal in synchronism with that 100-MHz reference signal to the semiconductor memory for testing for the presence or absence of a failure. All elements of the semiconductor memory are tested by the self-test circuit for a failure. If the self-test circuit finds a semiconductor memory element that fails to work properly, it provides a signal indicative of such failure to a failure counting circuit. This failure counting circuit counts the number of times the self-test circuit provides such a signal.

Abstract translation: 从半导体集成电路（SIC）器件外部向该SIC器件的信号输入端施加12.5MHz信号。 馈送来自输入端的12.5MHz信号的倍频电路，并将其频率为接收信号的频率（即100MHz）的倍数的参考信号传送到半导体存储器并进行自检 电路。 自测电路与该半导体存储器的100MHz参考信号同步地提供测试信号，以测试是否存在故障。 半导体存储器的所有元件都通过自检电路进行故障测试。 如果自检电路发现无法正常工作的半导体存储器元件，则向故障计数电路提供指示这种故障的信号。 该故障计数电路对自检电路提供这种信号的次数进行计数。

公开(公告)号：US5641699A

公开(公告)日：1997-06-24

申请号：US502557

申请日：1995-07-14

Applicant: Junji Hirase ,  Shin Hashimoto

Inventor： Junji Hirase ,  Shin Hashimoto

IPC: H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/108 ,  H01L27/105

Abstract: In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.

Abstract translation: 在半导体器件中，由绝缘部分隔开的集成电路区域的外周部分被定义为虚设单元区域，并且除了集成电路区域的外周部分之外的中心部分被定义为有源单元区域。 诸如DRAM，SRAM，EEPROM，掩模ROM的存储单元形成在活动单元区域中。 在集成电路区域中，设置多个单元形成区，分别由隔离限定。 每个具有场效应半导体元件的有源电池被提供在每个电池形成区域的有源电池区域中包括的区域中。 每个具有不可用作半导体元件的元件的虚拟单元设置在每个单元形成区域的虚拟单元区域中包括的区域中。 最后一个虚设单元被制成为具有至少具有栅极并且从与活性单元中的场效应半导体元件相同结构的P-N结部分中的至少一个排列的至少一个半导体元件的P-N缺乏的虚设单元。 所有虚拟细胞可能是缺乏伪细胞的P-N。 因此，防止了由于虚设单元区域中的栅极图案等的干扰而导致的缺乏虚设单元的P-N的绝缘缺陷。

公开(公告)号：US5584964A

公开(公告)日：1996-12-17

申请号：US453806

申请日：1995-05-30

Applicant: Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

Inventor： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

IPC: H01L21/3105 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/3105 ,  H01L27/108 ,  H01L27/105 ,  Y10S148/133 ,  Y10S438/978

Abstract: There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).

Abstract translation: 公开了一种制造半导体存储器件的方法。 在包括开关晶体管的半导体衬底上形成层间绝缘膜。 然后，形成到达开关晶体管的有源区的存储器节点图形。 通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值 平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。 然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。 然后，在BPSG膜上形成铝布线。 利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低 通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

公开(公告)号：US08679955B2

公开(公告)日：2014-03-25

申请号：US13202419

申请日：2010-02-10

Applicant: Shin Hashimoto ,  Katsushi Akita ,  Kensaku Motoki ,  Hideaki Nakahata ,  Shinsuke Fujiwara

Inventor： Shin Hashimoto ,  Katsushi Akita ,  Kensaku Motoki ,  Hideaki Nakahata ,  Shinsuke Fujiwara

IPC: H01L21/20

CPC classification number: H01L21/0262 ,  C30B25/02 ,  C30B29/16 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L33/007

Abstract: A method for forming an epitaxial wafer is provided as one enabling growth of a gallium nitride based semiconductor with good crystal quality on a gallium oxide region. In step S107, an AlN buffer layer 13 is grown. In step S108, at a time t5, a source gas G1 containing hydrogen, trimethylaluminum, and ammonia, in addition to nitrogen, is supplied into a growth reactor 10 to grow the AlN buffer layer 13 on a primary surface 11a. The AlN buffer layer 13 is so called a low-temperature buffer layer. After a start of film formation of the buffer layer 13, in step S109 supply of hydrogen (H2) is started at a time t6. At the time t6, H2, N2, TMA, and NH3 are supplied into the growth reactor 10. A supply amount of hydrogen is increased between times t6 and t7, and at the time t7 the increase of hydrogen is terminated to supply a constant amount of hydrogen. At the time t7, H2, TMA, and NH3 are supplied into the growth reactor 10.

Abstract translation: 提供了一种用于形成外延晶片的方法，其可以在氧化镓区域上使得能够以良好的晶体质量生长氮化镓基半导体。 在步骤S107中，生长AlN缓冲层13。 在步骤S108中，在时刻t5，将除了氮以外的氢，三甲基铝和氨的原料气G1供给到生长反应器10中，以在主面11a上生长AlN缓冲层13。 AlN缓冲层13被称为低温缓冲层。 在开始形成缓冲层13之后，在步骤S109中，在时刻t6开始供给氢（H2）。 在时间t6，H2，N2，TMA和NH3被供应到生长反应器10中。在时间t6和t7之间，氢的供应量增加，而在时间t7，氢的增加被终止以提供恒定的量 的氢。 在时间t7，将H2，TMA和NH3供应到生长反应器10中。

公开(公告)号：US08633514B2

公开(公告)日：2014-01-21

申请号：US13409798

申请日：2012-03-01

Applicant: Shin Hashimoto ,  Tatsuya Tanabe ,  Katsushi Akita ,  Hideaki Nakahata ,  Hiroshi Amano

Inventor： Shin Hashimoto ,  Tatsuya Tanabe ,  Katsushi Akita ,  Hideaki Nakahata ,  Hiroshi Amano

IPC: H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0

Abstract translation: 提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由AlXGa1-XN（0