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    Integrated circuit devices having a metal-insulator-metal (MIM) capacitor
    42.
    发明申请
    Integrated circuit devices having a metal-insulator-metal (MIM) capacitor 审中-公开
    具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件

    公开(公告)号：US20050161727A1

    公开(公告)日：2005-07-28

    申请号：US11083874

    申请日：2005-03-18

    申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L21/20

    CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

    摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

    摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。

    Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor
    44.
    发明授权
    Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor 有权
    形成具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件的方法

    公开(公告)号：US06884673B2

    公开(公告)日：2005-04-26

    申请号：US10160646

    申请日：2002-05-31

    申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

    摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

    摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。

    Methods for forming semiconductor device capacitors that include an adhesive spacer that ensures stable operation
    45.
    发明授权
    Methods for forming semiconductor device capacitors that include an adhesive spacer that ensures stable operation 有权
    用于形成半导体器件电容器的方法，其包括确保稳定操作的粘合剂间隔物

    公开(公告)号：US06667209B2

    公开(公告)日：2003-12-23

    申请号：US10350766

    申请日：2003-01-24

    申请人： Seok-Jun Won ,  Yong-Kuk Jeong

    发明人： Seok-Jun Won ,  Yong-Kuk Jeong

    IPC分类号： H01L218242

    CPC分类号： H01L27/10855 ,  H01L28/91

    摘要： In a method for forming capacitors of semiconductor devices, a contact plug penetrating an interlayer dielectric (ILD) is formed on a semiconductor substrate. A supporting layer, an etch stop layer, and a molding layer are sequentially formed on the semiconductor substrate where the contact plug is formed. The molding layer is patterned to form a molding pattern. At this time, the molding pattern has an opening exposing an etch stop layer over the contact plug. Next, an adhesive spacer is formed on sidewalls of the opening. The etch stop layer and the supporting layer, which are exposed through the opening where the adhesive spacer is formed, are successively patterned. Thus, the etch stop pattern and the supporting pattern are formed to expose the contact plug. A lower electrode and a sacrificial pattern are formed to sequentially fill a hole region surrounded by sidewalls of the adhesive spacer, the etch stop pattern, and the supporting pattern. After removing the molding pattern and the sacrificial pattern, the adhesive spacer is removed. At this time, the adhesive spacer is composed of a material having good adhesion and high etch selectivity with respect to the etch stop pattern and the lower electrode, preferably a titanium nitride layer.

    摘要翻译： 在形成半导体器件的电容器的方法中，在半导体衬底上形成穿透层间电介质（ILD）的接触插塞。 在形成有接触塞的半导体基板上依次形成支撑层，蚀刻停止层和成型层。 将成型层图案化以形成模制图案。 此时，模制图案具有暴露接触插塞上方的蚀刻停止层的开口。 接下来，在开口的侧壁上形成粘合隔离物。 通过形成粘合剂间隔物的开口暴露的蚀刻停止层和支撑层被连续地图案化。 因此，形成蚀刻停止图案和支撑图案以露出接触插塞。 形成下电极和牺牲图案以依次填充由粘合剂间隔物，蚀刻停止图案和支撑图案的侧壁包围的孔区域。 在去除模制图案和牺牲图案之后，去除粘合剂间隔物。 此时，粘合剂间隔物由相对于蚀刻停止图案和下部电极，优选氮化钛层的具有良好粘附性和高蚀刻选择性的材料构成。

    METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    48.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    制造半导体集成电路器件的方法

    公开(公告)号：US20110306198A1

    公开(公告)日：2011-12-15

    申请号：US13157615

    申请日：2011-06-10

    申请人： Yong-Kuk Jeong ,  Dong-Suk Shin ,  Jong-Hun Kim ,  Hyun-Kwan Yu ,  Ki-eun Kim

    发明人： Yong-Kuk Jeong ,  Dong-Suk Shin ,  Jong-Hun Kim ,  Hyun-Kwan Yu ,  Ki-eun Kim

    IPC分类号： H01L21/28

    CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method of fabricating a semiconductor integrated circuit device includes forming a gate pattern on a semiconductor substrate, the gate pattern having a gate insulation film and a gate electrode. A spacer is formed on sidewalls of the gate pattern. A silicide layer is formed by a silicide process on at least one portion of the semiconductor substrate exposed by the gate pattern and the spacer, the silicide layer being formed using a silicide process. A stress buffer layer is formed on a resultant structure having the silicide layer. A stress film is formed on the stress buffer layer.

    摘要翻译： 一种制造半导体集成电路器件的方法包括在半导体衬底上形成栅极图案，栅极图案具有栅极绝缘膜和栅电极。 在栅极图案的侧壁上形成间隔物。 硅化物层通过硅化物工艺在由栅极图案和间隔物暴露的半导体衬底的至少一部分上形成，硅化物层使用硅化物工艺形成。 在具有硅化物层的所得结构上形成应力缓冲层。 在应力缓冲层上形成应力膜。

    Methods of manufacturing semiconductor devices
    49.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US07867867B2

    公开(公告)日：2011-01-11

    申请号：US11593898

    申请日：2006-11-07

    申请人： Yong-kuk Jeong ,  Andrew-tae Kim ,  Dong-suk Shin

    发明人： Yong-kuk Jeong ,  Andrew-tae Kim ,  Dong-suk Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/823864 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

    摘要翻译： 制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。 使第一层间电介质层脱氢可以改变第一层间电介质层的应力。 特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。 还提供了包括脱氢层间电介质层的半导体器件。

    Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance
    50.
    发明申请
    Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance 有权
    形成具有低接触电阻的硅化源/漏极触点的场效应晶体管的方法

    公开(公告)号：US20090239344A1

    公开(公告)日：2009-09-24

    申请号：US12402816

    申请日：2009-03-12

    申请人： Yong Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    发明人： Yong Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    IPC分类号： H01L21/335 ,  H01L21/28

    CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

    摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。