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    Semiconductor device package and method for manufacturing the same
    45.
    发明授权
    Semiconductor device package and method for manufacturing the same 有权

    公开(公告)号：US12040287B2

    公开(公告)日：2024-07-16

    申请号：US17963067

    申请日：2022-10-10

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Hsing Kuo Tien ,  Chih-Cheng Lee

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/16

    CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/16

    Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.

    Package substrate, electronic device package and method for manufacturing the same
    48.
    发明授权
    Package substrate, electronic device package and method for manufacturing the same 有权

    公开(公告)号：US11239184B2

    公开(公告)日：2022-02-01

    申请号：US16899507

    申请日：2020-06-11

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wu Chou Hsu ,  Chih-Cheng Lee ,  Min-Yao Chen ,  Hsing Kuo Tien

    IPC: H01L23/552 ,  H01L23/64 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.

    Semiconductor package with chamfered pads
    50.
    发明授权
    Semiconductor package with chamfered pads 有权

    公开(公告)号：US11056435B2

    公开(公告)日：2021-07-06

    申请号：US15815351

    申请日：2017-11-16

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chung Chieh Chang ,  Ya Fang Chan ,  Chih-Cheng Lee

    IPC: H01L23/535 ,  H01L21/02 ,  H01L23/498 ,  H01L23/00

    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another. The second central axes of the first and second conductive elements are substantially co-linear in the second direction. The second central axis of the third conductive element is substantially parallel to and misaligned from the second central axes of the first and second conductive elements. The first chamfer and the second chamfer are separated by at least one of the first central axis and the second central axis of the first conductive element and are substantially asymmetric.

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