公开(公告)号：US09891853B1

公开(公告)日：2018-02-13

申请号：US15000626

申请日：2016-01-19

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Gurjeet S. Saund ,  Rakesh L. Notani ,  Robert E. Jeter

IPC: G06F3/06 ,  G11C7/22 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1689 ,  G11C7/222 ,  G11C2207/2254

Abstract: A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

公开(公告)号：US20170365034A1

公开(公告)日：2017-12-21

申请号：US15692469

申请日：2017-08-31

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

IPC: G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

公开(公告)号：US20170091100A1

公开(公告)日：2017-03-30

申请号：US14870272

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Peter F. Holland

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0831 ,  G06F1/3218 ,  G06F1/3265 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1028 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/08 ,  G09G2360/121 ,  Y02D10/13

Abstract: Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store data and a display control unit configured to retrieve data from the data storage device. The data storage device may be placed in a reduced power state that results in increased latencies for accessing data within the device. The display control unit is configured to monitor an amount of data available for processing within the display control unit. In response to determining the amount of data has fallen to a threshold level, and in anticipation of a forthcoming data access request, the display control unit conveys an indication that prevents the data storage device from entering or remaining in the reduced power state. Subsequently, the display control unit conveys a request for data to the data storage device which will not be in the reduced power state.

公开(公告)号：US09524261B2

公开(公告)日：2016-12-20

申请号：US13724955

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Benjamin K. Dodge

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/38 ,  G06F13/28 ,  H04L12/801

CPC classification number: G06F13/385 ,  G06F13/28 ,  H04L47/10

Abstract: Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Abstract translation: 在一致性点防止交易过度缓冲的系统和方法。 相干点使用前瞻机制来确定存储器控制器中是否有足够的信用来转发存储在IRQ中的未完成事务。 如果没有足够的积分，则相干点可以防止交换结构将附加事务转发到相干点。 通过防止IRQ中的过度缓冲，交换结构执行的事务的基于QoS的排序得以保留。

公开(公告)号：US09280503B2

公开(公告)日：2016-03-08

申请号：US13861696

申请日：2013-04-12

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Munetoshi Fukami

IPC: G06F13/37 ,  G06F13/36

CPC classification number: G06F13/37 ,  G06F13/36

Abstract: In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction.

Abstract translation: 在一个实施例中，仲裁器可以实现具有延迟加权重载机制的赤字加权循环方案。 所述延迟可以大于或等于所述织物时钟与不具有交易但具有未消耗权重（或交易速率的差别的另一措施）的一个或多个源相关联的较慢时钟的比率。 如果在延迟期间从一个或多个源提供事务，则可以防止权重的重新加载。 在一些实施例中，仲裁器可以被扩充以改善在一些接口上的带宽的使用，其中一些事务可能被限制一段时间。 仲裁器可以实现执行循环仲裁的第一个指针。 如果第一指针指示其事务被临时阻止的源，则第二指针可以从主指针的当前位置向前搜索以定位未阻塞的事务。

公开(公告)号：US09229896B2

公开(公告)日：2016-01-05

申请号：US13724886

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4059 ,  G06F2213/0038

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.

Abstract translation: 用于通过总线结构中的桥梁维护每个源的读取和写入事务顺序的系统和方法。 该桥提供从总线结构中的第一总线到第二总线的连接。 第一个总线具有读取和写入事务的单一路径，第二个总线具有用于读取和写入事务的独立路径。 该桥在SoC中为每个源保留一对计数器，以跟踪未完成的读写事务的数量。 如果相应的写计数器不为零，桥将阻止读事务被转发到第二总线，如果相应的读计数器不为零，桥将阻止写事务被转发到第二总线。

公开(公告)号：US09082118B2

公开(公告)日：2015-07-14

申请号：US13944462

申请日：2013-07-17

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Munetoshi Fukami ,  Kevin C. Wong

IPC: G06F17/50 ,  G06Q20/38 ,  G06Q20/24

CPC classification number: G06Q20/38 ,  G06F17/5045 ,  G06F17/505 ,  G06Q20/24

Abstract: Embodiments of a local interface unit are disclosed that may allow for managing credits and tokens as part of flow control method. The local interface unit may include a transmit unit and a receive unit. The transmit unit may be configured to receive credits and tokens, determine an available number of credits based on the number received tokens, determine an available number of tokens based on the number of received tokens, and send the available credits to an arbitration unit. The available credits may then be updated, by the transmit unit in response to receiving a selected transaction from the arbitration, and the transmit unit may then transmit the selected transaction, and update the available credits and the available tokens once the transaction has been sent. The receive unit may be configured to send credits and tokens to a transmit unit, and receive a transaction sent by a transmit unit.

Abstract translation: 公开了本地接口单元的实施例，其可以允许作为流控制方法的一部分来管理信用和令牌。 本地接口单元可以包括发送单元和接收单元。 发送单元可以被配置为接收信用和令牌，基于所接收的令牌的数量来确定可用的信用数量，基于接收到的令牌的数量确定令牌的可用数量，并将可用信用发送到仲裁单元。 然后可以通过发送单元响应于从仲裁接收到所选择的交易而更新可用信用，并且发送单元然后可以发送所选择的交易，并且一旦交易被发送，就更新可用信用和可用令牌。 接收单元可以被配置为向发送单元发送信用和令牌，并且接收由发送单元发送的交易。

公开(公告)号：US20150149673A1

公开(公告)日：2015-05-28

申请号：US14089237

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Jim J. Lin ,  Timothy R. Paaske ,  Ben D. Jarrett

IPC: G06F13/40 ,  G06F13/362

CPC classification number: G06F13/405 ,  G06F13/362 ,  G06F13/364 ,  G06F13/4027

Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。

公开(公告)号：US20150143044A1

公开(公告)日：2015-05-21

申请号：US14081549

申请日：2013-11-15

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US20140304441A1

公开(公告)日：2014-10-09

申请号：US13859000

申请日：2013-04-09

Applicant: APPLE INC.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Joseph P. Bratt ,  Kevin C. Wong ,  Manu Gulati ,  Rohit K. Gupta

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。