公开(公告)号：US20190089128A1

公开(公告)日：2019-03-21

申请号：US16180041

申请日：2018-11-05

Applicant: APPLE INC.

Inventor： Chin Han Lin ,  Weiping Li ,  Xiaofeng Fan

IPC: H01S5/183 ,  H01S5/042 ,  H01S5/42 ,  H01S5/026 ,  H01L29/15 ,  H01S5/187

CPC classification number: H01S5/18327 ,  H01L29/152 ,  H01S5/026 ,  H01S5/0425 ,  H01S5/18308 ,  H01S5/18311 ,  H01S5/18333 ,  H01S5/18369 ,  H01S5/187 ,  H01S5/2063 ,  H01S5/423 ,  H01S2301/176

Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

公开(公告)号：US20180342544A1

公开(公告)日：2018-11-29

申请号：US15994874

申请日：2018-05-31

Applicant: Apple Inc.

Inventor： Chiajen Lee ,  Xiaofeng Fan

IPC: H01L27/146

Abstract: One or more cross-wafer capacitors are formed in an electronic component, circuit, or device that includes stacked wafers. One example of such a device is a stacked image sensor. The image sensor can include two or more wafers, with two wafers that are bonded to each other each including a conductive segment adjacent to, proximate, or abutting a bonding surface of the respective wafer. The conductive segments are positioned relative to each other such that each conductive element forms a plate of a capacitor. A cross-wafer capacitor is formed when the two wafers are attached to each other.

公开(公告)号：US10079487B2

公开(公告)日：2018-09-18

申请号：US15175792

申请日：2016-06-07

Applicant: Apple Inc.

Inventor： Xiaofeng Fan ,  Xin Y. Zhang ,  Junjun Li

IPC: H02H3/22 ,  H02H9/04 ,  H02H1/00 ,  H05K1/02 ,  H01L27/02 ,  H02H3/20

CPC classification number: H02H9/046 ,  H01L27/0285 ,  H02H1/0007 ,  H02H3/20 ,  H02H9/041 ,  H05K1/0259

Abstract: An apparatus includes a device, a comparison circuit, and a switch. The device includes a first terminal coupled to a first power supply signal, and a second terminal coupled to a ground reference. The comparison circuit is configured to compare a first voltage level on the first power supply signal to a second voltage level of a second power supply signal, and enable the device in response to a determination that the first voltage level is greater than the second voltage level. The switch circuit is configured to couple a power supply terminal of the comparison circuit to the first power supply signal in response to determining that the first voltage level is greater than the second voltage level, and to couple the power supply terminal to the second power supply signal in response to determining that the first voltage level is less than the second voltage level.

公开(公告)号：US20180090526A1

公开(公告)日：2018-03-29

申请号：US15713520

申请日：2017-09-22

Applicant: Apple Inc.

Inventor： Shingo Mandai ,  Cristiano L. Niclass ,  Nobuhiro Karasawa ,  Xiaofeng Fan ,  Arnaud Laflaquiere ,  Gennadiy A. Agranov

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/369

CPC classification number: H01L27/14665 ,  G01S7/4861 ,  G01S7/4863 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14616 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02027 ,  H01L31/03529 ,  H01L31/107 ,  H04N5/35572 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/37452 ,  H04N5/3765 ,  H04N5/378

Abstract: A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.

公开(公告)号：US09653448B2

公开(公告)日：2017-05-16

申请号：US14533187

申请日：2014-11-05

Applicant: Apple Inc.

Inventor： Xin Yi Zhang ,  Xiaofeng Fan ,  Junjun Li

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L29/785

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

公开(公告)号：US09549099B2

公开(公告)日：2017-01-17

申请号：US13797851

申请日：2013-03-12

Applicant: Apple Inc.

Inventor： Xiaofeng Fan

IPC: H04N3/14 ,  H01L27/148 ,  H04N5/378 ,  H04N5/335 ,  H01L27/146 ,  H04N5/3745 ,  H04N5/357

CPC classification number: H04N3/155 ,  H01L27/14609 ,  H01L27/14806 ,  H04N5/335 ,  H04N5/3575 ,  H04N5/37452 ,  H04N5/378

Abstract: A method for performing correlated double sampling for a sensor, such as an image sensor. The method includes collecting a first charge corresponding to a first parameter, transferring the first charge to a first storage component, transferring the first charge from the first storage component to a second storage component, resetting the first storage component, transferring the first charge from the second storage component to the first storage component, and reading the first storage component to determine the first charge. The method may be implemented in electronic devices including image sensors.

Abstract translation: 用于对诸如图像传感器的传感器执行相关双重采样的方法。 该方法包括收集对应于第一参数的第一电荷，将第一电荷转移到第一存储组件，将第一电荷从第一存储组件转移到第二存储组件，复位第一存储组件， 第二存储组件到第一存储组件，以及读取第一存储组件以确定第一充电。 该方法可以在包括图像传感器的电子设备中实现。

公开(公告)号：US09503622B2

公开(公告)日：2016-11-22

申请号：US14202256

申请日：2014-03-10

Applicant: Apple Inc.

Inventor： Tongbi T. Jiang ,  Xiaofeng Fan

IPC: H04N5/225 ,  H04N5/374

CPC classification number: H04N5/2253 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2924/10157 ,  H01L2924/15151 ,  H04N5/2257 ,  H04N5/374

Abstract: A CMOS imager assembly may include an integrated circuit (IC) having an active-pixel image sensor that is mounted on a printed circuit board (PCB) substrate using flip chip packaging technology. The IC and the PCB may be physically and electrically connected to each other through multiple electrically conductive connectors. An underfill material (which may include an anti-reflective material) may, during assembly, be introduced around the connectors in the space between the IC and the PCB. A chemical or physical discontinuity on the integrated circuit may, during assembly, prevent the underfill material from entering an area framed by the discontinuity, which may include the pixel array of the image sensor. The discontinuity may include a dam-like structure built up on the IC, a trench-like structure created on the IC, or a low surface tension material that has been applied to the surface of the IC.

Abstract translation: CMOS成像器组件可以包括具有使用倒装芯片封装技术安装在印刷电路板（PCB）衬底上的有源像素图像传感器的集成电路（IC）。 IC和PCB可以通过多个导电连接器物理和电连接。 在组装期间，底部填充材料（其可以包括抗反射材料）可以在IC和PCB之间的空间中的连接器周围引入。 在组装期间，集成电路上的化学或物理不连续性可以在组装期间防止底部填充材料进入由不连续构成的区域，其可以包括图像传感器的像素阵列。 不连续性可以包括在IC上构建的坝状结构，在IC上形成的沟槽状结构或已经施加到IC的表面的低表面张力材料。

公开(公告)号：US09356061B2

公开(公告)日：2016-05-31

申请号：US13959362

申请日：2013-08-05

Applicant: Apple Inc.

Inventor： Xiaofeng Fan ,  Philip H. Li ,  Chung Chun Wan ,  Anup K. Sharma ,  Xiangli Li

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14685

Abstract: A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region.

Abstract translation: 图像传感器中的像素可以包括设置在一个基板中的光电检测器和存储区域，或者设置在一个基板中的光电检测器和另一个基板中的存储区域。 掩埋的光屏蔽设置在光电检测器和存储区之间。 诸如浮动扩散的感测区域可以与存储区域相邻，其中掩埋的光屏蔽件设置在光电检测器和存储和感测区域之间。 当光电检测器和存储区域设置在分离的基板中时，可以通过掩埋的光屏蔽形成垂直栅极，并且用于开始从光电检测器和存储区域传输电荷。 形成在垂直栅极附近或周围的转移通道提供用于电荷从光电检测器转移到存储区域的通道。

公开(公告)号：US20160056146A1

公开(公告)日：2016-02-25

申请号：US14684872

申请日：2015-04-13

Applicant: Apple Inc.

Inventor： Junjun Li ,  Xin Yi Zhang ,  Xiaofeng Fan

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/74 ,  H01L29/10 ,  H01L27/06 ,  H01L27/088 ,  H01L29/744

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L27/0635 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7416 ,  H01L29/7436 ,  H01L29/744

Abstract: In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared.

Abstract translation: 在一个实施例中，ESD保护电路可以包括可以与STI结合的SCR并联的STI结合的SCR和门控SCR。 门控SCR可以在半导体衬底的平面中垂直于STI结合的SCR。 在一个实施例中，门控SCR可以比STI结合的SCR更快地触发并且更快地触发。 STI结合的SCR可以形成用于ESD事件的主电流路径。 因此可以形成具有对ESD事件的快速响应的低容性负载。 在一个实施例中，两个SCR的阳极可以共享。

公开(公告)号：US20160043126A1

公开(公告)日：2016-02-11

申请号：US14886029

申请日：2015-10-17

Applicant: Apple Inc.

Inventor： Xiaofeng Fan

IPC: H01L27/146

CPC classification number: H04N5/369 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14634 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14843 ,  H01L29/7827 ,  H04N5/335 ,  H04N9/045

Abstract: A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

Abstract translation: 具有光电二极管芯片和晶体管阵列芯片的垂直堆叠图像传感器。 光电二极管芯片包括至少一个光电二极管，并且传输门从光电二极管芯片的顶表面垂直延伸。 图像传感器还包括堆叠在光电二极管芯片顶部的晶体管阵列芯片。 晶体管阵列芯片包括控制电路和存储节点。 图像传感器还包括垂直堆叠在晶体管阵列芯片上的逻辑芯片。 传输门将数据从至少一个光电二极管传送到晶体管阵列芯片，逻辑芯片选择性地激活垂直传输门，复位栅极，源极跟随器栅极和行选择栅极。