公开(公告)号：US20240371613A1

公开(公告)日：2024-11-07

申请号：US18654221

申请日：2024-05-03

Applicant: Applied Materials, Inc.

Inventor： Muhannad Mustafa ,  Janisht Golcha ,  Sanjeev Baluja ,  Srinivas Gandikota ,  Yixiong Yang

IPC: H01J37/32 ,  C23C16/455

Abstract: Semiconductor manufacturing processing chambers having an RF isolator between the support ring and the showerhead and/or an RF gasket between the showerhead and the gas funnel are described. A cap insert with a cap housing around the cap insert is on the gas funnel and an RF feed is in contact with the showerhead. A substrate support can be included and may have an RF return path directed through the substrate support.

公开(公告)号：US20240332008A1

公开(公告)日：2024-10-03

申请号：US18126583

申请日：2023-03-27

Applicant: Applied Materials, Inc.

Inventor： Geetika Bajaj ,  Tianyi Huang ,  Hsin-Jung Yu ,  Yixiong Yang ,  Srinivas Gandikota ,  Chi-Chou Lin ,  Pei Hsuan Lin

IPC: H01L21/02 ,  H01L21/28

CPC classification number: H01L21/02321 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/28229

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.

公开(公告)号：US12104243B2

公开(公告)日：2024-10-01

申请号：US17348849

申请日：2021-06-16

Applicant: Applied Materials, Inc.

Inventor： Annamalai Lakshmanan ,  Jacqueline S. Wrench ,  Feihu Wang ,  Yixiong Yang ,  Joung Joo Lee ,  Srinivas Gandikota ,  Sang-heum Kim ,  Zhebo Chen ,  Gang Shen

IPC: C23C14/02 ,  C23C14/06 ,  C23C14/16 ,  C23C14/58 ,  C23C16/02 ,  C23C16/06 ,  C23C16/42 ,  C23C16/455 ,  C23C16/52 ,  C23C16/56

CPC classification number: C23C16/0281 ,  C23C14/021 ,  C23C14/025 ,  C23C14/0682 ,  C23C14/16 ,  C23C14/5886 ,  C23C16/0227 ,  C23C16/06 ,  C23C16/42 ,  C23C16/45527 ,  C23C16/52 ,  C23C16/56

Abstract: Methods and apparatus for processing a substrate is provided herein. For example, a method for processing a substrate comprises depositing a silicide layer within a feature defined in a layer on a substrate, forming one of a metal liner layer or a metal seed layer atop the silicide layer within the feature via depositing at least one of molybdenum (Mo) or tungsten (W) using physical vapor deposition, and depositing Mo using at least one of chemical vapor deposition or atomic layer deposition atop the at least one of the metal liner layer or the metal seed layer, without vacuum break.

公开(公告)号：US12100595B2

公开(公告)日：2024-09-24

申请号：US17347786

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Jianqiu Guo ,  Seshadri Ganguli ,  Steven C. H. Hung ,  Srinivas Gandikota

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545

Abstract: A sacrificial sealing layer is formed on a high-κ metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-κ metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-κ metal oxide layer to form a dipole region.

公开(公告)号：US12051734B2

公开(公告)日：2024-07-30

申请号：US18076958

申请日：2022-12-07

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Steven C. H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Yong Yang

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/517 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28568 ,  H01L29/518

Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

公开(公告)号：US20240183033A1

公开(公告)日：2024-06-06

申请号：US18074197

申请日：2022-12-02

Applicant: Applied Materials, Inc.

Inventor： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Elizabeth Mao ,  Chi-Chou Lin

IPC: C23C16/455 ,  C23C16/34 ,  H01L21/3205 ,  H01L21/768

CPC classification number: C23C16/45527 ,  C23C16/34 ,  H01L21/32051 ,  H01L21/76843

Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.

公开(公告)号：US11997849B2

公开(公告)日：2024-05-28

申请号：US17329484

申请日：2021-05-25

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Pradeep K. Subrahmanyan ,  Srinivas Gandikota

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/8234 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/823437 ,  H01L21/823462 ,  H10B43/27

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

公开(公告)号：US11961734B2

公开(公告)日：2024-04-16

申请号：US17729643

申请日：2022-04-26

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang ,  Steven C. H. Hung

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L21/02247 ,  H01L21/02043 ,  H01L21/02274 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/67023 ,  H01L21/67207

Abstract: A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

公开(公告)号：US20240087899A1

公开(公告)日：2024-03-14

申请号：US17941557

申请日：2022-09-09

Applicant: Applied Materials, Inc.

Inventor： Zhihui Liu ,  Seshadri Ganguli ,  Tianyi Huang ,  Yixiong Yang ,  Srinivas Gandikota ,  Yuanhua Zheng ,  Yongjing Lin ,  Keyur Karandikar ,  Elizabeth Mao

IPC: H01L21/225 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/225 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0234 ,  H01L29/401

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one or more layers or surfaces of layers in the metal gate stack. The radical treatment may be performed once or multiple times during the methods described herein. The radical treatment comprises flowing one or more of nitrogen radicals (N2*) and hydrogen radicals (H*) over the surface of the metal gate stack.

公开(公告)号：US20240063064A1

公开(公告)日：2024-02-22

申请号：US17891923

申请日：2022-08-19

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Tianyi Huang ,  Tengzhou Ma ,  Seshadri Ganguli

IPC: H01L21/8238 ,  H01L29/51 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L29/517 ,  H01L21/76829 ,  H01L21/324 ,  H01L21/0228

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.