INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE
    41.
    发明申请
    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE 有权
    集成电路接地屏蔽结构

    公开(公告)号:US20130147023A1

    公开(公告)日:2013-06-13

    申请号:US13313240

    申请日:2011-12-07

    IPC分类号: H01L23/552

    摘要: The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译: 本公开提供了一种集成电路(IC)装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽(PGS)结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。

    DE-EMBEDDING ON-WAFER DEVICES
    43.
    发明申请
    DE-EMBEDDING ON-WAFER DEVICES 有权
    嵌入式嵌入式设备

    公开(公告)号:US20120146680A1

    公开(公告)日:2012-06-14

    申请号:US12963511

    申请日:2010-12-08

    IPC分类号: G01R31/00

    摘要: A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.

    摘要翻译: 提供传输线。 在一个实施例中,传输线包括衬底,衬底内的阱,阱上的屏蔽层以及屏蔽层上的多个中间金属层,多个中间金属层通过多个通孔耦合。 传输线还包括多个中间金属层上的顶部金属层。 还公开了用于去嵌入晶片装置和晶片的测试结构。

    Method and apparatus for de-embedding on-wafer devices
    45.
    发明授权
    Method and apparatus for de-embedding on-wafer devices 有权
    用于去嵌入晶片装置的方法和装置

    公开(公告)号:US07954080B2

    公开(公告)日:2011-05-31

    申请号:US12042606

    申请日:2008-03-05

    IPC分类号: G06F17/50

    CPC分类号: G01R31/2884 H01L22/34

    摘要: A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

    摘要翻译: 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件(“DUT”)的固有特性的一组参数。