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46 条记录 (耗时 0.025 秒)

    DE-EMBEDDING ON-WAFER DEVICES
    2.
    发明申请
    DE-EMBEDDING ON-WAFER DEVICES 有权
    嵌入式嵌入式设备

    公开(公告)号：US20120146680A1

    公开(公告)日：2012-06-14

    申请号：US12963511

    申请日：2010-12-08

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Sa-Lly Liu

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Sa-Lly Liu

    IPC分类号： G01R31/00

    CPC分类号： G01R31/2601 ,  G01R1/0491 ,  G01R31/2644 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/5602 ,  H01L22/34

    摘要： A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.

    摘要翻译： 提供传输线。 在一个实施例中，传输线包括衬底，衬底内的阱，阱上的屏蔽层以及屏蔽层上的多个中间金属层，多个中间金属层通过多个通孔耦合。 传输线还包括多个中间金属层上的顶部金属层。 还公开了用于去嵌入晶片装置和晶片的测试结构。

    Slot-shielded coplanar strip-line compatible with CMOS processes
    3.
    发明授权
    Slot-shielded coplanar strip-line compatible with CMOS processes 有权
    与CMOS工艺兼容的插槽屏蔽共面带状线

    公开(公告)号：US09087840B2

    公开(公告)日：2015-07-21

    申请号：US12917285

    申请日：2010-11-01

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    IPC分类号： H01L23/14 ,  H01L23/522 ,  H01L23/66 ,  H01L27/06

    CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L27/0629 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

    摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

    STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING
    4.
    发明申请
    STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING 有权
    具有电容耦合的高K变压器的结构和方法

    公开(公告)号：US20130099352A1

    公开(公告)日：2013-04-25

    申请号：US13280786

    申请日：2011-10-25

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/5222 ,  H01F17/0013 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/552 ,  H01L23/642 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有集成电路（IC）器件的半导体衬底; 布置在半导体衬底上并与IC器件耦合的互连结构; 以及设置在半导体衬底上并集成在互连结构中的变压器。 变压器包括第一导电特征; 与所述第一导电特征电感耦合的第二导电特征; 电连接到第一导电特征的第三导电特征; 以及电连接到第二导电特征的第四导电特征。 第三和第四导电特征被设计和配置为电容耦合以增加变压器的耦合系数。

    TRANSFORMER WITH BYPASS CAPACITOR
    5.
    发明申请
    TRANSFORMER WITH BYPASS CAPACITOR 有权
    带旁路电容器的变压器

    公开(公告)号：US20120146741A1

    公开(公告)日：2012-06-14

    申请号：US12963701

    申请日：2010-12-09

    申请人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Ying-Ta Lu ,  Chin-Wei Kuo ,  Ho-Hsiang Chen

    发明人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Ying-Ta Lu ,  Chin-Wei Kuo ,  Ho-Hsiang Chen

    IPC分类号： H03H7/42 ,  H01L21/00

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F2017/0086 ,  H01L23/5223 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors.

    摘要翻译： 电子器件包括串联连接并形成在半导体衬底上的金属层中的第一，第二和第三电感器。 第一和第二电感器具有彼此的互感。 第二和第三电感器具有彼此的互感。 第一电容器具有连接到第一节点的第一电极。 第一节点电导耦合在第一和第二电感器之间。 第二电容器具有连接到第二节点的第二电极。 第二节点电导耦合在第二和第三电感器之间。

    Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes
    9.
    发明申请
    Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes 有权
    Slot-Shielded Coplanar Strip-line兼容CMOS工艺

    公开(公告)号：US20120104575A1

    公开(公告)日：2012-05-03

    申请号：US12917285

    申请日：2010-11-01

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    IPC分类号： H01L23/14

    CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L27/0629 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

    摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

    STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR
    10.
    发明申请
    STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR 有权
    FISHBONE差分电容器的结构和方法

    公开(公告)号：US20130228894A1

    公开(公告)日：2013-09-05

    申请号：US13411052

    申请日：2012-03-02

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    IPC分类号： H01L27/06 ,  H01L21/768

    CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L28/88 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.

    摘要翻译： 本发明提供集成电路。 集成电路包括具有由第一轴线和垂直于第一轴线的第二轴线限定的表面的基板; 以及设置在基板上的电容器结构。 电容器结构包括第一导电元件; 对称地配置在第一导电部件的相对侧上的第二导电部件和第三导电部件。 第一，第二和第三导电部件通过相应的介电材料彼此分离。