利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

150 条记录 (耗时 0.03 秒)

    Non volatile embedded memory with poly protection layer
    41.
    发明授权
    Non volatile embedded memory with poly protection layer 有权
    非易失性嵌入式存储器，具有多层保护层

    公开(公告)号：US06787416B2

    公开(公告)日：2004-09-07

    申请号：US10253039

    申请日：2002-09-24

    申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

    发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

    摘要翻译： 本发明包括用于形成非易失性存储器单元和外围设备的装置和方法，对电子俘获层的损害降低，并且可选地在CMOS处理期间减少热暴露。 在权利要求书，说明书和附图中描述了本发明的特定方面。

    Method for forming embedded non-volatile memory
    42.
    发明授权
    Method for forming embedded non-volatile memory 有权
    嵌入式非易失性存储器的形成方法

    公开(公告)号：US06559010B1

    公开(公告)日：2003-05-06

    申请号：US10003320

    申请日：2001-12-06

    申请人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

    发明人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.

    摘要翻译： 描述了一种用于形成非易失性存储器的方法，包括将衬底划分成至少存储器阵列区域和逻辑器件区域。 首先在衬底上形成氧化物/氮化物/氧化物（ONO）层，并且通过位线光刻工艺在ONO层上形成光致抗蚀剂层，并在衬底上进行位线离子注入工艺以形成多个 位线结构。 然后，通过字线照片条件沉积第一多晶硅层以形成多个字线。 互补金属氧化物半导体（CMOS）ONO层用于存储电荷，并且ONO层仅被光致抗蚀剂层触及一次。 此外，存储器阵列区域和逻辑器件区域的分离的调整照相条件可以产生安全的氧化物厚度，以通过使用自对准硅化物处理来解决位线到位线之间的泄漏路径的问题。

    Interposer and manufacturing method thereof
    47.
    发明授权
    Interposer and manufacturing method thereof 有权
    插件及其制造方法

    公开(公告)号：US08692284B2

    公开(公告)日：2014-04-08

    申请号：US13484140

    申请日：2012-05-30

    申请人： Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

    发明人： Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

    IPC分类号： H01L29/72

    CPC分类号： H05K3/185 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K1/115 ,  H05K3/0023 ,  H05K3/426 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

    摘要翻译： 本发明的一个实施例提供了一种内插器的制造方法，包括：提供具有第一表面，第二表面和至少连接第一表面与第二表面的通孔的半导体衬底; 在第一表面，第二表面和通孔的内壁上电聚合聚合物层; 以及在所述电涂层聚合物层上形成布线层，其中所述布线层经由所述通孔的内壁从所述第一表面延伸到所述第二表面。 本发明的另一实施例提供一种插入器。

    Package structure and method for making the same
    48.
    发明授权
    Package structure and method for making the same 有权
    包装结构和制作方法

    公开(公告)号：US08624351B2

    公开(公告)日：2014-01-07

    申请号：US13117151

    申请日：2011-05-27

    申请人： Chien-Hung Liu ,  Shu-Ming Chang

    发明人： Chien-Hung Liu ,  Shu-Ming Chang

    IPC分类号： H01L29/02 ,  H01L21/78

    CPC分类号： H01L21/6835 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/11

    摘要： A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

    摘要翻译： 公开了一种包括非导电衬底，导电元件，钝化层，接合侧，导电层，焊料和焊料掩模的封装结构。 导电元件设置在非导电衬底的表面上，由无源元件和相应的电路构成。 钝化完全覆盖导电元件和非导电衬底，使得导电元件夹在钝化层和非导电衬底之间。 导电层覆盖接合侧，露出相应电路的一部分，延伸超过接合侧并与相应的电路电连接。 完全覆盖接合侧的焊料掩模和导电层选择性地暴露设置在接合侧外侧并与导电层电连接的焊料。

    Manufacturing-process equipment
    49.
    发明授权
    Manufacturing-process equipment 失效
    制造加工设备

    公开(公告)号：US08575791B2

    公开(公告)日：2013-11-05

    申请号：US12971466

    申请日：2010-12-17

    申请人： Wen-Yuh Jywe ,  Jing-Chung Shen ,  Chin-Tien Yang ,  Chien-Hung Liu ,  Jau-Jiu Ju ,  Chia-Hung Wu ,  Chun-Chieh Huang ,  Lili Duan ,  Yuan-Chin Lee

    发明人： Wen-Yuh Jywe ,  Jing-Chung Shen ,  Chin-Tien Yang ,  Chien-Hung Liu ,  Jau-Jiu Ju ,  Chia-Hung Wu ,  Chun-Chieh Huang ,  Lili Duan ,  Yuan-Chin Lee

    IPC分类号： G01B11/02 ,  H02K41/02

    CPC分类号： B23K26/0853

    摘要： A manufacturing-process equipment has a platform assembly, a measurement feedback assembly and a laser-working assembly. The platform assembly has a base and a hybrid-moving platform. The base has a mounting frame. The hybrid-moving platform is mounted on the base and has a long-stroke moving stage and a piezo-driven micro-stage. The long-stroke moving stage has a benchmark set and a driving device. The piezo-driven micro-stage is connected to the long-stroke moving stage and has a working platform. The measurement feedback assembly is securely mounted on the platform assembly and has a laser interferometer, a reflecting device and a signal-receiving device. The laser-working assembly is mounted on the platform assembly, is electrically connected to the measurement feedback assembly and has a laser direct-writing head, a controlling interface device and a positioning interface device.

    摘要翻译： 制造过程设备具有平台组件，测量反馈组件和激光加工组件。 平台组件具有基座和混合动力平台。 底座有一个安装架。 混合动力平台安装在基座上，具有长行程移动台和压电驱动微型平台。 长冲程移动台具有基准组和驱动装置。 压电驱动微型平台连接到长行程移动台，并具有工作平台。 测量反馈组件牢固地安装在平台组件上，并具有激光干涉仪，反射装置和信号接收装置。 激光加工组件安装在平台组件上，电连接到测量反馈组件，并具有激光直写头，控制接口装置和定位接口装置。

    CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    50.
    发明申请
    CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    芯片包装结构及其形成方法

    公开(公告)号：US20130020693A1

    公开(公告)日：2013-01-24

    申请号：US13548663

    申请日：2012-07-13

    申请人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

    发明人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

    IPC分类号： H01L29/02 ,  H01L21/50 ,  H01L21/02

    CPC分类号： B81B3/0051 ,  B81B2201/025 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.

    摘要翻译： 公开了一种用于形成芯片封装结构的芯片封装结构和方法。 至少一个块形成在盖的表面上，盖安装在其上形成有感测装置的基板上，用于覆盖感测装置，并且该块设置在盖和感测装置之间。 在本发明中，该块安装在盖上，不需要蚀刻盖以形成突出部分，因此本发明的方法简单且成本低。