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178 条记录 (耗时 0.031 秒)

    Interconnect structure
    42.
    发明授权
    Interconnect structure 有权
    互连结构

    公开(公告)号：US07928570B2

    公开(公告)日：2011-04-19

    申请号：US12424843

    申请日：2009-04-16

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/538

    CPC分类号： H01L21/76847 ,  H01L21/76805 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure is disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.

    摘要翻译： 公开了互连结构。 在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

    INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER
    46.
    发明申请
    INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER 失效
    使用Mn-VIIIB合金衬里的互连结构

    公开(公告)号：US20110180309A1

    公开(公告)日：2011-07-28

    申请号：US12693637

    申请日：2010-01-26

    申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Kazumichi Tsumura ,  Takamasa Usui

    发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Kazumichi Tsumura ,  Takamasa Usui

    IPC分类号： H05K1/09 ,  H05K3/10

    CPC分类号： H01L21/76846 ,  H01L21/4814 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.

    摘要翻译： 至少包括第VIIIB族元素层和CuMn合金层的金属衬垫堆积在电介质层的沟槽内。 铜沉积在金属衬垫上并被平坦化以形成导电互连结构，其可以是金属线，金属通孔或其组合。 沉积的铜和金属衬垫在平坦化之前或之后退火。 通过第VIIIB族元素层吸收Mn原子以形成包含Mn和VIIIB族元素中的至少一种的金属合金衬里。 金属合金衬里内的Mn在退火期间与氧结合形成MnO，其作为氧扩散的强势垒，从而提高导电互连结构的可靠性。

    CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS
    49.
    发明申请
    CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 失效
    创造不同深度的VIAS和TRENCHES

    公开(公告)号：US20110101538A1

    公开(公告)日：2011-05-05

    申请号：US12610624

    申请日：2009-11-02

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

    摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 还提供了由此制成的半导体结构。