公开(公告)号：US07124503B1

公开(公告)日：2006-10-24

申请号：US09655893

申请日：2000-09-06

Applicant: Delin Li ,  Jay D. Baker ,  Myron Lemecha

Inventor： Delin Li ,  Jay D. Baker ,  Myron Lemecha

IPC: H01K3/10

CPC classification number: H05K3/4038 ,  H05K3/062 ,  H05K3/4084 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2203/0361 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for forming connections within a multi-layer electronic circuit board 10 which allows for the selective, efficient, and reliable interconnection between at least one conductive layer and a ground plane or layer.

Abstract translation: 一种用于在多层电子电路板10内形成连接的方法，其允许至少一个导电层与接地平面或层之间的选择性，有效和可靠的互连。

公开(公告)号：US06952047B2

公开(公告)日：2005-10-04

申请号：US10611390

申请日：2003-07-01

Applicant: Delin Li

Inventor： Delin Li

IPC: H01L25/065 ,  H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member is placed on top of the first microelectronic element and is used to support a second microelectronic element. The second microelectronic element is arranged with the conductive member in a top and bottom position. The second microelectronic element is then also connected by leads from contacts on the second microelectronic element to pads and terminals on the circuitized substrate. The conductive member is then connected to a third pad or set of pads on the substrate. An encapsulant material may be deposited so as to encapsulate the leads and at least one surface of the microelectronic elements. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.

Abstract translation: 一种制造多个半导体芯片封装的方法以及所得到的芯片封装组件。 该方法包括提供具有端子和引线的电路化基板。 第一微电子元件与衬底一起布置，微电子元件上的触点连接到衬底。 导电构件放置在第一微电子元件的顶部上，并用于支撑第二微电子元件。 第二微电子元件布置成导电构件处于顶部和底部位置。 第二微电子元件然后还通过引线从第二微电子元件上的触点连接到电路化基板上的焊盘和端子。 然后将导电构件连接到衬底上的第三衬垫或一组衬垫。 可以沉积密封剂材料以便封装引线和微电子元件的至少一个表面。 密封剂材料然后被固化，从而限定了可以被分成单个芯片封装的芯片组件的复合材料。

公开(公告)号：US09023253B2

公开(公告)日：2015-05-05

申请号：US13787997

申请日：2013-03-07

Applicant: Xiaoli Liu ,  Ran Guo ,  Delin Li

Inventor： Xiaoli Liu ,  Ran Guo ,  Delin Li

IPC: H01B1/02 ,  H01B1/22 ,  H01L31/0224

CPC classification number: C09D5/24 ,  H01B1/16 ,  H01L31/022425 ,  H01L31/18 ,  Y02E10/50

Abstract: The present invention provides a conductive paste characterized by a crystal-based corrosion binder being combined with a glass frit and mixed with a metallic powder and an organic carrier. Methods for preparing each components of the conductive paste are disclosed including several embodiments of prepare Pb—Te—O-based crystal corrosion binder characterized by melting temperatures in a range of 440° C. to 760° C. and substantially free of any glass softening transition upon increasing temperature. Method for preparing the conductive paste includes mixture of the components and a grinding process to ensure all particle sizes in a range of 0.1 to 5.0 microns. Method of applying the conductive paste for the formation of a front electrode of a semiconductor device is presented to illustrate the effectiveness of the crystal-based corrosion binder in transforming the conductive paste to a metallic electrode with good ohmic contact with semiconductor surface.

Abstract translation: 本发明提供了一种导电性糊料，其特征在于将结晶型腐蚀粘合剂与玻璃料组合并与金属粉末和有机载体混合。 公开了制备导电浆料各组分的方法，其包括制备Pb-Te-O基结晶腐蚀粘合剂的几个实施方案，其特征在于在440℃至760℃的范围内的熔融温度，并且基本上不含任何玻璃软化 温度升高时过渡。 制备导电浆料的方法包括组分的混合物和研磨过程，以确保所有粒径在0.1至5.0微米的范围内。 提出了施加用于形成半导体器件的前电极的导电膏的方法，以说明晶体腐蚀粘合剂在将导电膏转化为具有与半导体表面的欧姆接触良好的金属电极的有效性。

公开(公告)号：US20130240363A1

公开(公告)日：2013-09-19

申请号：US13849643

申请日：2013-03-25

Applicant: Delin Li

Inventor： Delin Li

IPC: H01L21/02

CPC classification number: H01L31/18 ,  C25D5/10 ,  C25D5/48 ,  H01L21/02104 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  H01L31/206 ,  Y02E10/541 ,  Y02P70/521

Abstract: The present invention relates to CIGS solar cell fabrication. The invention discloses a method for fabricating CIGS thin film solar cells using a roll-to-roll apparatus. The invention discloses method to fabricate semiconductor thin film Cu(InGa)(SeS)2 by sequentially electroplating a stack of multiple precursor layers comprising of copper, indium, gallium, and selenium elements or their alloys followed by selenization at a temperature between 450° C. and 700° C.

Abstract translation: 本发明涉及CIGS太阳能电池制造。 本发明公开了一种使用卷对卷装置制造CIGS薄膜太阳能电池的方法。 本发明公开了通过依次电镀由铜，铟，镓和硒元素或其合金组成的多个前体层的堆叠，然后在450℃的温度下进行硒化来制造半导体薄膜Cu（InGa）（SeS）2的方法 和700℃

公开(公告)号：US06274819B1

公开(公告)日：2001-08-14

申请号：US09387808

申请日：1999-09-01

Applicant: Delin Li ,  Jay DeAvis Baker ,  Achyuta Achari ,  Brenda Joyce Nation ,  John Trublowski

Inventor： Delin Li ,  Jay DeAvis Baker ,  Achyuta Achari ,  Brenda Joyce Nation ,  John Trublowski

IPC: H05K111

CPC classification number: H05K3/361 ,  H05K1/0293 ,  H05K1/117 ,  H05K1/118 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/053 ,  H05K2201/09127 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2203/0228 ,  H05K2203/175 ,  Y10T29/49124 ,  Y10T29/49169 ,  Y10T29/4973 ,  Y10T29/49732

Abstract: An article and method for making and repairing connections between first and second circuits, such as flex circuits. The article 10 includes: a flexible dielectric substrate 12 having first and second edges 14/16, and a plurality of conductive circuit traces 18 arranged on or within the substrate, wherein each of the traces extends from proximate the first edge 14 to proximate the second edge 16. Each of the circuit traces 18 includes: a first connection feature 20 disposed proximate the first edge 14; a second connection feature 22 disposed proximate the second edge 16; and at least one third connection feature 24 disposed between the first and second edges 14/16. Each of the first, second, and third connection features 20/22/24 is a plated through hole, a plated blind via, or a mounting pad. This article 10 may be used to connect together the first and second circuits 50/60 using the first and second connection features 20/22, such as by soldering. If either of the two circuits needs to be subsequently detached (e.g., because of a component failure), the article 10 may be cut so as to present a set of third connection features 24 to which a new replacement circuit may be connected.

公开(公告)号：US06270354B1

公开(公告)日：2001-08-07

申请号：US09387202

申请日：1999-08-31

Applicant: Delin Li ,  Jay DeAvis Baker ,  Achyuta Achari ,  Brenda Joyce Nation ,  John Trublowski

Inventor： Delin Li ,  Jay DeAvis Baker ,  Achyuta Achari ,  Brenda Joyce Nation ,  John Trublowski

IPC: H01R1200

Abstract: A multi-connectable printed circuit assembly, comprising: (a) a printed circuit substrate 11 having a first edge 22 and first and second edge regions 44/55, wherein at least the first edge region 44 is defined along the first edge 22; (b) a first array 77 of electrical connection features 66 disposed on or within the substrate proximate the first edge region 44; (c) a second array 88 of electrical connection features 66 disposed on or within the substrate proximate the second edge region 55, wherein the second array 88 is substantially a duplication or a mirror image of the first array 77; and (d) a plurality of circuit traces 99 disposed on or within the substrate such that each electrical connection feature 66 of the first array 77 is connected by one of the circuit traces 99 to a corresponding electrical connection feature 66 of the second array 88.