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    TAPERED VIA AND MIM CAPACITOR
    41.
    发明申请
    TAPERED VIA AND MIM CAPACITOR 有权
    TAPERED通过和MIM电容器

    公开(公告)号：US20120275080A1

    公开(公告)日：2012-11-01

    申请号：US13096850

    申请日：2011-04-28

    申请人： JAMES S. DUNN ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： JAMES S. DUNN ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01G4/33 ,  H01G7/00

    CPC分类号： H01L28/40 ,  H01G4/228 ,  H01G4/33

    摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

    摘要翻译： 描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。 描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。

    Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture
    43.
    发明授权
    Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture 有权
    免费金属绝缘体金属（MIM）电容器和制造方法

    公开(公告)号：US08191217B2

    公开(公告)日：2012-06-05

    申请号：US12535769

    申请日：2009-08-05

    申请人： James S. Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： James S. Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01G7/00

    CPC分类号： H01G4/33 ,  H01G4/1209 ,  H01G4/232 ,  H01G4/38 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49156 ,  H01L2924/00

    摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

    摘要翻译： 同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。 该方法包括在电介质材料上沉积底板; 在底板上沉积低k介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器 第一厚度。

    Design structure for an on-chip high frequency electro-static discharge device
    44.
    发明授权
    Design structure for an on-chip high frequency electro-static discharge device 失效
    片上高频静电放电装置的设计结构

    公开(公告)号：US07768762B2

    公开(公告)日：2010-08-03

    申请号：US12144084

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H02H7/20 ,  H02H9/00

    CPC分类号： G06F17/5068 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

    摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。 每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。 所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封，以为所述集成电路提供静电放电保护。

    Method for forming an on-chip high frequency electro-static discharge device
    45.
    发明授权
    Method for forming an on-chip high frequency electro-static discharge device 失效
    用于形成片上高频静电放电装置的方法

    公开(公告)号：US07759243B2

    公开(公告)日：2010-07-20

    申请号：US12144089

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76808 ,  H01L21/7682 ,  H01L27/0248

    摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.

    摘要翻译： 描述了在集成电路上形成片上高频静电放电装置的方法。 在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。 在封盖的第一介电层上沉积第二介电层。 第一硬掩模介电层沉积在第二介电层上。 通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。 至少一个通孔围绕腔沟槽形成穿过第二电介质层。 在所述至少一个通孔中的每一个周围形成金属沟槽。 在空腔沟槽上形成释放开口。 在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

    METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY
    46.
    发明申请
    METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY 失效
    选择性反向掩模平面化和互连结构的方法

    公开(公告)号：US20100127395A1

    公开(公告)日：2010-05-27

    申请号：US12323512

    申请日：2008-11-26

    申请人： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

    摘要翻译： 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

    INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
    50.
    发明申请
    INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT 有权
    无线电集成电路的互连结构和设计结构

    公开(公告)号：US20120292741A1

    公开(公告)日：2012-11-22

    申请号：US13560446

    申请日：2012-07-27

    申请人： Timothy Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Timothy Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L23/522 ,  G06F17/50

    CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/016 ,  H01L28/20 ,  H01L28/40

    摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

    摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。