公开(公告)号：US5663090A

公开(公告)日：1997-09-02

申请号：US496722

申请日：1995-06-29

申请人： Charles H. Dennison ,  Randhir P. S. Thakur

发明人： Charles H. Dennison ,  Randhir P. S. Thakur

IPC分类号： H01L21/02 ,  H01L21/205 ,  H01L21/70

CPC分类号： H01L28/84 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L28/90 ,  Y10S438/906 ,  Y10S438/964

摘要： An embodiment of the present discloses a thermal process for forming hemispherical grained silicon on a silicon material by the steps of: heating the silicon material to a steady state temperature; exposing the silicon material to a hydrogen containing ambient; and causing a decreasing temperature differential of the silicon material while exposing the silicon material to a silicon hydride gas. This embodiment is accomplished by using a thermal cycle having a temperature ramp up period, a temperature steady state period during at least a portion of which the H.sub.2 ambient is present and temperature ramp down period during at least a portion of which the diluted silicon hydride gas is present. A second embodiment discloses a process for forming a hemispherical grained silicon surface on at least one capacitor plate made of silicon material, by increasing the temperature of the capacitor plate in an H.sub.2 containing ambient; exposing a surface of the capacitor plate's silicon material to a cleaning gas (such as GeH.sub.4, NF.sub.3, using ultraviolet light in the presence of ozone gas, vapor hydrofluoric acid silicon hydride gas, and H.sub.2); and decreasing the temperature of the capacitor plate while exposing the capacitor plate to a silicon hydride gas.

摘要翻译： 本发明的一个实施方案公开了一种通过以下步骤在硅材料上形成半球形晶粒硅的热处理：将硅材料加热至稳态温度; 将硅材料暴露于含氢环境中; 并且在使硅材料暴露于硅氢化物气体的同时导致硅材料的温差降低。 该实施例通过使用具有温度升高周期的热循环，在至少一部分H2环境存在的温度稳态期间和在其至少一部分稀释的氢化硅气体 存在。 第二实施例公开了一种通过在含氢气氛中增加电容器板的温度来在由硅材料制成的至少一个电容器板上形成半球形晶粒硅表面的工艺; 将电容器板的硅材料的表面暴露于清洁气体（例如GeH 4，NF 3，在存在臭氧气体的情况下使用紫外线，蒸气氢氟酸氢化物气体和H 2）; 并且在电容器板暴露于硅氢气体的同时降低电容器板的温度。

公开(公告)号：US5658381A

公开(公告)日：1997-08-19

申请号：US439022

申请日：1995-05-11

申请人： Randhir P. S. Thakur ,  Michael Nuttall

发明人： Randhir P. S. Thakur ,  Michael Nuttall

IPC分类号： C30B1/02 ,  H01L21/02 ,  C30B31/22

CPC分类号： H01L28/82 ,  C30B1/023 ,  C30B29/06 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

摘要： Hemispherical grain (HSG) silicon for a semiconductor device, is formed by: introducing a crystallization nucleus into a silicon material; and converting the silicon material into the HSG silicon by promoting the growth of the crystallization nucleus during a high vacuum anneal. An embodiment of the present invention is a semiconductor device having hemispherical grain (HSG) silicon, where the HSG silicon comprises a silicon material converted into the HSG silicon from the growth of at least one implanted crystallization nucleus.

摘要翻译： 半导体器件的半球形晶粒（HSG）硅通过：将结晶核引入硅材料中而形成; 并通过在高真空退火期间促进结晶核的生长而将硅材料转化成HSG硅。 本发明的一个实施方案是具有半球形晶粒（HSG）硅的半导体器件，其中HSG硅包括从至少一个注入的结晶核的生长转化成HSG硅的硅材料。

公开(公告)号：US5561612A

公开(公告)日：1996-10-01

申请号：US245422

申请日：1994-05-18

申请人： Randhir P. S. Thakur

发明人： Randhir P. S. Thakur

IPC分类号： C23C16/46 ,  G05B17/02 ,  G05D23/19 ,  H05B6/50

CPC分类号： C23C16/46 ,  G05B17/02 ,  G05D23/1917

摘要： Temperature nonuniformity across a semiconductor wafer during both the transient and steady state of a typical rapid thermal processing (RTP) cycle has been a deterrent in using RTP in many VLSI unit processes. The present invention consists of a three-dimensional mathematical model to study the temperature variation across a wafer in an RTP oven for given lamp power settings, during both the transient and steady state of a typical thermal cycle and control a heating lamp back by a computer program. The simulation package has been written in FORTRAN, and the validity of various models have been checked by performing a series of oxidation experiments.

摘要翻译： 在典型的快速热处理（RTP）周期的瞬态和稳态期间半导体晶片的温度不均匀性在许多VLSI单元过程中使用RTP一直是一个威慑。 本发明由三维数学模型组成，用于在典型热循环的瞬态和稳态期间研究用于给定灯功率设置的RTP烘箱中晶片的温度变化，并且通过计算机控制加热灯 程序。 模拟软件包已经在FORTRAN中编写，并通过一系列氧化实验检查了各种模型的有效性。

公开(公告)号：US5382533A

公开(公告)日：1995-01-17

申请号：US79322

申请日：1993-06-18

申请人： Aftab Ahmad ,  Randhir P. S. Thakur

发明人： Aftab Ahmad ,  Randhir P. S. Thakur

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L21/265

CPC分类号： H01L29/512 ,  H01L21/28176 ,  H01L29/518 ,  H01L29/6659 ,  Y10S438/91

摘要： A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si.sub.3 N.sub.4 and SF.

摘要翻译： 用于抑制半微米MOS器件中的热电子的方法，其中在硅衬底的表面上形成栅极氧化物和栅电极，并且使用栅电极作为掩模将源极和漏极区域离子注入到硅衬底中。 该方法包括在栅电极上方和衬底的源极和漏极区上形成二氧化硅层，然后将阻挡层形成元件引入到二氧化硅层中以在界面处形成热电子的薄屏障区 在硅衬底和二氧化硅之间。 在本发明的一个优选实施方案中，通过在快速热处理器中加热晶片并且在含氮气体存在下在升高的温度下将氮气引入二氧化硅中达预定时间。 含氮气体可以选自三氟化氮，氨和一氧化二氮。 在本发明的替代实施例中，氟原子作为唯一的阻挡层形成元件（氟化硅）或在形成薄氮化硅区之前被引入到硅衬底中。 氟原子在硅衬底中形成良好的强硅 - 氟键，从而进一步增强热电子抑制。 在第三实施例中，氮和氟在快速热处理器中反应以形成Si 3 N 4和SF的复合势垒层。

公开(公告)号：US5376593A

公开(公告)日：1994-12-27

申请号：US999335

申请日：1992-12-31

申请人： Gurtej S. Sandhu ,  Randhir P. S. Thakur

发明人： Gurtej S. Sandhu ,  Randhir P. S. Thakur

IPC分类号： H01L21/306 ,  H01L21/314 ,  H01L21/318 ,  H01L21/321 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/02046 ,  H01L21/02049 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/32105 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832

摘要： A method for fabricating semiconductor wafers is disclosed, wherein a semiconductor substrate is provided in a chamber. Subsequently, a first silicon nitride layer is formed in situ under high pressure superjacent the substrate by introducing a gas containing nitrogen, preferably NH.sub.3 combined with N.sub.2, at a temperature within the range of 850.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds. This results in the first layer having a thickness in the approximate range of 5 .ANG. to 30 .ANG.. A semiconductor film is then deposited in situ under high pressure superjacent the first silicon nitride layer, preferably by means of Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"). In an alternate embodiment of the present invention, this is accomplished by either Low Pressure Chemical Vapor Deposition ("LPCVD") or Molecular Beam Epitaxy ("MBE"). The thickness of the film is in the approximate range of 10 .ANG. to 40 .ANG.. Consequently, the film is transformed in situ under high pressure into a second silicon nitride layer by introducing a gas containing nitrogen, preferably NH.sub.3 combined with N.sub.2, at a temperature substantially within the range of 850.degree. C. to 1150.degree. C. applied for approximately 10 to 60 seconds. The thickness of the second silicon nitride layer is substantially in the range of the thickness of the film. In one embodiment of the present invention, only a portion of the film is transformed into a second silicon nitride layer, thereby creating a remainder of the film subjacent the second silicon nitride layer. In this embodiment, the thickness of the second silicon nitride layer is less than the thickness of the film. Finally, a second semiconductor film is deposited superjacent the second layer in situ under high pressure. In one alternate embodiment of the present invention, a pair of silicon dioxide layers are grown between the step of providing a semiconductor substrate and the step of depositing a second semiconductor film.

公开(公告)号：US5340765A

公开(公告)日：1994-08-23

申请号：US106503

申请日：1993-08-13

申请人： Charles H. Dennison ,  Randhir P. S. Thakur

发明人： Charles H. Dennison ,  Randhir P. S. Thakur

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/82 ,  H01L27/10817 ,  H01L28/84 ,  H01L28/90 ,  Y10S148/138 ,  Y10S438/964

摘要： The present invention develops a container capacitor by forming a conductively doped polysilicon plug between a pair of neighboring parallel conductive word lines; forming a planarized tetra-ethyl-ortho-silicate (TEOS) insulating layer over the parallel conductive word lines and the plug; forming a planarized borophosphosilicate glass (BPSG) insulating layer over the planarized tetra-ethyl-ortho-silicate (TEOS) insulative layer; forming an opening into both insulating layers to expose an upper surface of the plug, the opening thereby forming a container shape; forming first, second and third layers of conductively doped amorphous silicon into the container shape while simultaneously bleeding oxygen into the amorphous silicon; forming individual container structures having inner and outer surfaces and thereby exposing the BPSG insulating layer; removing the BPSG insulating layer thereby exposing the outer surface of the container structures; converting the exposed inner and outer surfaces of amorphous silicon into hemispherical grained polysilicon by subjecting the structures to a high vacuum anneal; forming a nitride insulating layer adjacent and coextensive the conductive container structure; and forming a second conductively doped polysilicon layer superjacent and coextensive the nitride insulating layer.

摘要翻译： 本发明通过在一对相邻的平行导电字线之间形成导电掺杂多晶硅插塞来开发容器电容器; 在平行的导电字线和插头上形成平面化的四乙基原硅酸盐（TEOS）绝缘层; 在平坦化的四乙基原硅酸盐（TEOS）绝缘层上形成平坦化的硼磷硅酸盐玻璃（BPSG）绝缘层; 在两个绝缘层中形成开口以露出插塞的上表面，从而形成容器形状; 将导电掺杂的非晶硅的第一，第二和第三层形成为容器形状，同时将氧气渗入到非晶硅中; 形成具有内表面和外表面的单个容器结构，从而暴露BPSG绝缘层; 去除BPSG绝缘层，从而暴露容器结构的外表面; 通过对结构进行高真空退火，将非晶硅的暴露的内表面和外表面转化成半球状的多晶硅; 形成与所述导电容器结构相邻并共同延伸的氮化物绝缘层; 以及形成第二导电掺杂多晶硅层，所述第二导电掺杂多晶硅层与所述氮化物绝缘层相邻并共同延伸。

公开(公告)号：US20080210671A1

公开(公告)日：2008-09-04

申请号：US11508781

申请日：2006-08-23

申请人： Dean Jennings ,  Abhilash J. Mayur ,  Timothy N. Thomas ,  Vijay Parihar ,  Vedapuram S. Achutharaman ,  Randhir P. S. Thakur

发明人： Dean Jennings ,  Abhilash J. Mayur ,  Timothy N. Thomas ,  Vijay Parihar ,  Vedapuram S. Achutharaman ,  Randhir P. S. Thakur

IPC分类号： B23K26/00

CPC分类号： B23K26/0738 ,  B23K26/0613 ,  B23K26/0676 ,  H01L21/268 ,  H01L29/7833 ,  Y10T117/1016

摘要： A dynamic surface anneal apparatus for annealing a semiconductor workpiece has a workpiece support for supporting a workpiece, an optical source and scanning apparatus for scanning the optical source and the workpiece support relative to one another along a fast axis. The optical source includes an array of laser emitters arranged generally in successive rows of the emitters, the rows being transverse to the fast axis. Plural collimating lenslets overlie respective ones of the rows of emitters and provide collimation along the fast axis. The selected lenslets have one or a succession of optical deflection angles corresponding to beam deflections along the fast axis for respective rows of emitters. Optics focus light from the array of laser emitters onto a surface of the workpiece to form a succession of line beams transverse to the fast axis spaced along the fast axis in accordance with the succession of deflection angles.

摘要翻译： 用于退火半导体工件的动态表面退火装置具有用于支撑工件的工件支撑件，用于沿着快轴相对于彼此扫描光源和工件支撑件的光源和扫描装置。 光源包括大致以发射器的连续行布置的激光发射器的阵列，这些行横向于快轴。 多个准直的小透镜叠加在发射器排中的相应行上，并沿着快轴提供准直。 所选择的小透镜具有对应于沿着快轴的光束偏转的相应行发射器的一个或一系列光学偏转角。 将来自激光发射器阵列的光聚焦到工件的表面上，以根据偏转角的顺序形成一系列沿着快轴间隔开的快轴的线束。

公开(公告)号：US06927445B2

公开(公告)日：2005-08-09

申请号：US09921423

申请日：2001-08-02

申请人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

发明人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC分类号： H01L21/02 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

摘要翻译： 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用耐蚀刻材料覆盖交替层，并蚀刻交替层，从而形成具有 波纹状。

公开(公告)号：US06812530B2

公开(公告)日：2004-11-02

申请号：US09875501

申请日：2001-06-04

申请人： Klaus Florian Schuegraf ,  Randhir P. S. Thakur

发明人： Klaus Florian Schuegraf ,  Randhir P. S. Thakur

IPC分类号： H01L2976

CPC分类号： H01L21/3215 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28273 ,  H01L21/76889 ,  H01L27/115

摘要： The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

摘要翻译： 本发明包括堆叠的半导体器件，包括栅极堆叠，字线，PROM，导电互连线以及用于形成这种结构的方法。 一方面，本发明包括形成导线的方法，包括：a）形成多晶硅层; 形成针对多晶硅层的硅化物层; b）在硅化物层内提供电导率增强杂质; 以及c）将所述多晶硅层和所述硅化物层设置成导线形状。 在另一方面，本发明包括可编程只读存储器件，其包括：a）衬底上的第一介电层; b）在第一介电层上的浮栅; c）浮置栅极上的第二电介质层; d）在第二介电层上的导电线; 以及e）所述导电线上的金属硅化物层，所述金属硅化物层包含III族掺杂剂或V族掺杂剂。

公开(公告)号：US06806572B2

公开(公告)日：2004-10-19

申请号：US10277688

申请日：2002-10-22

申请人： Randhir P. S. Thakur

发明人： Randhir P. S. Thakur

IPC分类号： H01L2334

CPC分类号： H01L21/76831 ,  H01L21/28525 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76879 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

摘要翻译： 提供了一种使用掺杂硅改善接触的新方法和结构。 这些结构被集成到几个较高级别的实施例中。 改进的接触具有低接触电阻率。 因此，在IGFET器件和随后的金属化层之间提供改进的结。 通过使用硅 - 锗（Si-Ge）合金获得改进。 该合金可以通过将锗沉积到基底上并随后对接触进行退火或通过选择性地将预成型合金沉积到接触开口中而形成。 上述优点结合相对较少的工艺步骤。