公开(公告)号：US20080238599A1

公开(公告)日：2008-10-02

申请号：US11729311

申请日：2007-03-27

Applicant: Francois Hebert ,  Ming Sun

Inventor： Francois Hebert ,  Ming Sun

IPC: H01F17/04 ,  H01F27/28

CPC classification number: H01L23/645 ,  H01L23/5227 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/1902 ,  H01L2924/3025 ,  Y10T29/4902 ,  Y10T29/49075 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.

Abstract translation: 公开了一种具有电感器基板和翻转到电感器基板上的功率集成电路的芯片级功率转换器封装。 电感器基板包括其上形成有平面螺旋电感器的高电阻率基板。

公开(公告)号：US20070035906A1

公开(公告)日：2007-02-15

申请号：US11503357

申请日：2006-08-10

Applicant: Richard Harris ,  Richard Blanchard ,  Francois Hebert

Inventor： Richard Harris ,  Richard Blanchard ,  Francois Hebert

IPC: H02H9/06

CPC classification number: H02H9/025

Abstract: Improved electrical transient blocking is provided with a transient blocking unit (TBU) having a partial disconnect capability. A TBU is an arrangement of voltage controlled switches that normally conducts, but switches to a disconnected state in response to an above-threshold input transient. Partial disconnection improves the power handling capability of a TBU by preventing thermal damage to the TBU. Partial TBU disconnection can be implemented to keep power dissipation in the TBU below a predetermined level Pmax, thereby avoiding thermal damage to the TBU by keeping the TBU temperature below a temperature limit Tmax. Alternatively, partial TBU disconnection can be implemented to keep TBU temperature below Tmax using direct temperature sensing and feedback.

Abstract translation: 提供了具有部分断开能力的瞬态阻塞单元（TBU）的改进的电气瞬态阻塞。 TBU是通常导通的电压控制开关的布置，但是响应于高于阈值的输入瞬变而切换到断开状态。 部分断开通过防止TBU的热损坏提高了TBU的功率处理能力。 可以实施部分TBU断开以将TBU中的功率消耗降低到预定水平P max以下，从而通过将TBU温度保持在温度下限T max以下来避免对TBU的热损伤， SUB>。 或者，可以使用直接温度感测和反馈来实现部分TBU断开以将TBU温度保持在T 以下。

公开(公告)号：US20060158812A1

公开(公告)日：2006-07-20

申请号：US11331836

申请日：2006-01-12

Applicant: Richard Harris ,  Francois Hebert

Inventor： Richard Harris ,  Francois Hebert

IPC: H02H3/22

CPC classification number: H02H9/025 ,  H01L27/0266 ,  H02H9/04

Abstract: A transient blocking unit (TBU) having improved damage resistance is provided. A TBU includes two or more depletion mode transistors arranged to provide a low series impedance in normal operation and a high series impedance when the input current exceeds a predetermined threshold. At least one of the TBU transistors is a protecting device having a shunt circuit element connected in parallel with its channel. When the TBU is in its high impedance state, the shunt circuit element provides a current path, thereby decreasing terminal voltages on at least one of the TBU transistors. The shunt element can be a discrete or integrated resistor, a current source including a transistor, or an appropriately engineered device parasitic.

Abstract translation: 提供了具有改善的耐损伤性的瞬态阻断单元（TBU）。 TBU包括两个或多个耗尽型晶体管，其布置成在正常操作中提供低串联阻抗，并且当输入电流超过预定阈值时包括高串联阻抗。 TBU晶体管中的至少一个是具有与其沟道并联连接的分流电路元件的保护器件。 当TBU处于高阻抗状态时，分流电路元件提供电流路径，从而减小至少一个TBU晶体管的端电压。 分路元件可以是分立或集成的电阻器，包括晶体管的电流源或者适当设计的器件寄生的。

公开(公告)号：US20060098364A1

公开(公告)日：2006-05-11

申请号：US11270062

申请日：2005-11-08

Applicant: Richard Harris ,  Francois Hebert

Inventor： Richard Harris ,  Francois Hebert

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H02H5/042 ,  H02H5/044 ,  H02H9/025 ,  H02H9/046

Abstract: An apparatus and method for enhanced transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device such that the p- and n-channel devices mutually switch off to block the transient. The apparatus has an enhancer circuit for applying an enhancement bias to a gate terminal of at least one of the depletion mode n-channel devices of the TBU to reduce a total resistance Rtot of the apparatus. Alternatively, the apparatus has an enhancement mode NMOS transistor and a TBU connected thereto to help provide an enhancement bias to a gate terminal of the enhancement mode NMOS.

Abstract translation: 一种用于增强瞬态阻塞的装置和方法，其采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）。 执行互连，使得瞬态改变p沟道器件的偏置电压V P和N沟道器件的偏置电压V N n N，使得p - 和n通道设备相互关闭以阻止瞬态。 该装置具有增强器电路，用于向TBU中的至少一个耗尽型n沟道器件的栅极端子施加增强偏置，以减小器件的总电阻R tht。 或者，该装置具有增强型NMOS晶体管和与其连接的TBU，以帮助向增强型NMOS的栅极端提供增强偏置。

公开(公告)号：US06797549B2

公开(公告)日：2004-09-28

申请号：US10272688

申请日：2002-10-15

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L2100

CPC classification number: H01L29/402 ,  H01L29/42376 ,  H01L29/7835

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.

Abstract translation: 提供具有在栅极附近的漏极区域中具有减小的电场的栅极延伸的高压MOS晶体管。 高压MOS晶体管包括第一和第二栅极层以及栅极层之间的介电层。 第一和第二栅极层电耦合在一起并形成晶体管的栅极。 第二栅极层在电介质和栅极氧化物层上方的晶体管的漏极上延伸以形成栅极延伸。 门极延伸通过为晶体管的漏极和栅极之间的电压降提供一个宽的面积来减小漏极中的峰值电场。 电介质层还通过在栅极和漏极之间提供绝缘来减小栅极附近的漏极中的峰值电场。 漏极中较低的电场降低了载流子的冲击产生速率。 本发明的高电压MOS晶体管可以在不使用BiCMOS和CMOS工艺中的附加处理步骤的情况下制造，所述工艺使用双重多晶硅层和用于形成电容器的电介质层。

公开(公告)号：US06720228B1

公开(公告)日：2004-04-13

申请号：US09691949

申请日：2000-10-18

Applicant: John F. Sevic ,  Francois Hebert

Inventor： John F. Sevic ,  Francois Hebert

IPC: H01L21336

CPC classification number: H03F1/301

Abstract: A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the current mirror transistor is modified whereby the drain-to-gate voltage can be positive, and the lightly doped drain region in the lateral n-channel reference transistor is shortened and dopant concentration increased to increase the electric field of the reference transistor to provide the hot carrier injection degradation characteristics similar to the main transistor. Additionally, the gate length of the reference transistor can be shortened to effect the hot carrier injection degradation.

Abstract translation: 修改用于RF放大器晶体管的电流镜偏置电路，由此电流镜的参考晶体管跟踪RF晶体管中的热载流子劣化。 对电流镜晶体管的栅极偏置被修改，从而漏极 - 栅极电压可以是正的，并且横向n沟道参考晶体管中的轻掺杂漏极区域被缩短并且掺杂剂浓度增加以增加参考晶体管的电场 提供类似于主晶体管的热载流子注入降解特性。 此外，可以缩短参考晶体管的栅极长度，以实现热载流子注入降级。

公开(公告)号：US6091110A

公开(公告)日：2000-07-18

申请号：US430530

申请日：1999-10-29

Applicant: Francois Hebert ,  Szehim Ng

Inventor： Francois Hebert ,  Szehim Ng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.

Abstract translation: 一种制造MOSFET晶体管的方法，所得结构具有形成在栅极电极和漏极区域之间的凹槽中的漏极 - 栅极反馈电容屏蔽。 屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。 该方法不需要复杂或昂贵的处理，因为需要一个附加的非临界掩模，用于产生凹槽的选择性蚀刻。

公开(公告)号：US5841166A

公开(公告)日：1998-11-24

申请号：US711495

申请日：1996-09-10

Applicant: Pablo E. D'Anna ,  Francois Hebert

Inventor： Pablo E. D'Anna ,  Francois Hebert

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/7816 ,  H01L29/1087 ,  H01L29/41741 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/1095 ,  H01L29/41 ,  H01L29/42368 ,  Y10S148/126

Abstract: An IGFET device (lateral DMOS transistor) with reduced cell dimensions which is especially suitable for RF and microwave applications, includes a semiconductor substrate having an epitaxial layer with a device formed in a surface of the epitaxial layer. A sinker contact is provided from the surface to the epitaxial layer to the substrate for use in grounding the source region to the grounded substrate. The sinker contact is aligned with the source region and spaced from the width of the channel region whereby lateral diffusion in forming the sinker contact does not adversely affect the pitch of the cell structure. The reduced pitch increases output power and reduces parasitic capacitance whereby the device is well-suited for low side switches and as an RF/microwave power transistor.

公开(公告)号：US5385861A

公开(公告)日：1995-01-31

申请号：US213144

申请日：1994-03-15

Applicant: Rashid Bashir ,  Francois Hebert ,  Datong Chen

Inventor： Rashid Bashir ,  Francois Hebert ,  Datong Chen

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/76

CPC classification number: H01L21/76227 ,  H01L21/763 ,  Y10S148/05

Abstract: A novel device isolation scheme for separating active regions on a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. According to this scheme, shallow and deep trenches are etched into the semiconductor substrate. A layer of nitride is deposited over the entire substrate followed by a layer of poly-silicon. Oxide spacers on the poly-silicon and a photoresist mask is aligned within the oxide spacers, thereby permitting the selective etching of the poly-silicon layer. The poly-silicon layer overlying the active regions of the semiconductor substrate are etched away. Then an oxidation step is performed such that the poly-silicon layer filling the shallow trenches is oxidized while the poly-silicon filling the deep trenches remains unoxidized. The alignment of the photoresist becomes highly non-critical because of the use of the oxide spacers and fully walled junctions are provided.

Abstract translation: 公开了一种用于通过组合场氧化物形成和沟槽隔离来分离半导体衬底上的有源区的新型器件隔离方案。 根据该方案，将浅沟槽和深沟槽蚀刻到半导体衬底中。 一层氮化物沉积在整个衬底上，随后是一层多晶硅。 在多晶硅和光致抗蚀剂掩模之间的氧化物间隔物在氧化物间隔物内对准，从而允许多晶硅层的选择性蚀刻。 覆盖半导体衬底的有源区的多晶硅层被蚀刻掉。 然后执行氧化步骤，使得填充浅沟槽的多晶硅层被氧化，而填充深沟槽的多晶硅保持未氧化。 由于使用氧化物间隔物并且提供了完全的壁结，因此光致抗蚀剂的取向变得非常关键。

公开(公告)号：US08836064B2

公开(公告)日：2014-09-16

申请号：US13530809

申请日：2012-06-22

Applicant: Eric S. Lee ,  Michael I-Shan Sun ,  Francois Hebert

Inventor： Eric S. Lee ,  Michael I-Shan Sun ,  Francois Hebert

IPC: H01L31/0232

CPC classification number: H01L31/02327 ,  H01L21/0272 ,  H01L31/02162 ,  H01L31/101 ,  H01L31/103 ,  H01L31/18

Abstract: Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In certain embodiments, a short duration soft bake is performed. Alternatively, or additionally, temperature cycling is performed. Alternatively, or additionally, photolithography is performed using a photomask that includes one or more dummy corners, dummy islands and/or dummy rings. Each of the aforementioned embodiments form and/or increase a number of micro-cracks in the dielectric optical coating not covering the photodetector sensor region, thereby enabling an accelerated lift-off process and an increased process margin. Alternatively, or additionally, a portion of the photomask can include chamfered corners so that the dielectric optical coating includes chamfered corners, which improves the thermal reliability of the dielectric optical coating.

Abstract translation: 本文描述了包括用于塑造其光谱响应的介电光学涂层的光传感器以及以加速剥离过程并增加工艺裕度的方式制造这种光传感器的方法。 在某些实施例中，执行短持续时间的软烘烤。 或者或另外，进行温度循环。 或者或附加地，使用包括一个或多个虚拟角，虚拟岛和/或虚拟环的光掩模来执行光刻。 上述实施例中的每一个形成和/或增加了不覆盖光电检测器传感器区域的电介质光学涂层中的数量的微裂纹，由此实现加速的剥离过程和增加的工艺余量。 或者或另外，光掩模的一部分可以包括倒角，使得介电光学涂层包括倒角，这改善了介电光学涂层的热可靠性。