公开(公告)号：US6031293A

公开(公告)日：2000-02-29

申请号：US299330

申请日：1999-04-26

申请人： Min-Chih Hsuan ,  Fu-Tai Liou

发明人： Min-Chih Hsuan ,  Fu-Tai Liou

IPC分类号： H01K23/48

CPC分类号： H01L23/3192 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/0613 ,  H01L2224/06179 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48464 ,  H01L24/45 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14

摘要： A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.

摘要翻译： 一种硅芯片上的无封装焊盘结构，其包括硅芯片上表面上的多个金属焊盘和覆盖硅芯片上表面的钝化层。 钝化层具有在金属焊盘区域正上方的多个开放空腔，用于暴露每个金属焊盘的一部分。 开口腔的直径在接近钝化层的上表面时变小，并且在金属垫区域附近增大。

公开(公告)号：USRE35111E

公开(公告)日：1995-12-05

申请号：US984084

申请日：1992-11-30

申请人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02

摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the rust metal silicide layer from damage.

摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护防锈金属硅化物层免受损坏。

公开(公告)号：US5424571A

公开(公告)日：1995-06-13

申请号：US302374

申请日：1994-09-08

申请人： Fu-Tai Liou

发明人： Fu-Tai Liou

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L29/6659 ,  Y10S257/90

摘要： A method for forming field effect devices having lightly doped drain regions requires only a single dope and implant step. After patterning of the polycrystalline silicon gates, sloped sidewall spacers are formed alongside the gates. These spacers have a relatively linear slope from the top corners of the polycrystalline silicon gates to the substrate. A single implant of dopant results in heavily doped regions beyond the sidewall spacers with more lightly, and shallowly, doped regions next to the channel.

摘要翻译： 用于形成具有轻掺杂漏极区域的场效应器件的方法仅需要单个掺杂和注入步骤。 在多晶硅栅极图形化之后，沿着栅极形成倾斜的侧壁间隔物。 这些间隔物从多晶硅栅极的顶角到衬底具有相对线性的斜率。 单个掺杂剂的注入导致超过侧壁间隔物的重掺杂区域，在沟道旁边具有更轻的和浅的掺杂区域。

公开(公告)号：US5410176A

公开(公告)日：1995-04-25

申请号：US66939

申请日：1993-05-24

申请人： Fu-Tai Liou ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Fusen E. Chen

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/324 ,  H01L21/316 ,  H01L21/477

CPC分类号： H01L21/76227

摘要： A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

摘要翻译： 公开了一种用于在集成电路中形成隔离结构的方法以及如此形成的结构。 在通过提供掩蔽层来实现表面的有源区域的定义之后，将凹陷蚀刻到暴露位置，达到绝缘隔离结构的最终厚度顺序的深度。 二氧化硅或另一种绝缘非晶材料的侧壁间隔物沿着凹槽的侧壁设置，其中凹部的底部露出硅。 硅的选择性外延生长然后在凹陷内形成一层硅，优选为凹陷深度的一半的厚度。 外延硅被热氧化，用热二氧化硅填充凹陷，具有与表面的活性区基本上共面的顶表面。 根据替代实施例，侧壁间隔件的形成可以以这样的方式进行，使得较窄的凹槽保持用侧壁间隔物的材料填充。

公开(公告)号：US5371410A

公开(公告)日：1994-12-06

申请号：US90294

申请日：1993-07-12

申请人： Fusen E. Chen ,  Fu-Tai Liou

发明人： Fusen E. Chen ,  Fu-Tai Liou

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L21/76847 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/97

摘要： A method for forming aluminum metallization for contacting a conductive element in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, a first aluminum alloy layer is formed within the contact, optionally with a barrier layer between it and the underlying electrode. An etch stop layer is formed thereover, of a material which has a low etch rate to an aluminum etchant species. A second, thicker, aluminum alloy layer is formed thereover. The second aluminum layer is etched until the etch stop layer is reached; the mask for defining the metal line may have an edge within the dimensions of the contact opening. After removal of the exposed etch stop layer, a timed etch removes the first aluminum alloy layer, without exposing the bottom of the contact. The metal line may thus be safely formed, without requiring an enclosure around the contact opening. According to an alternate embodiment, conductive or semiconductive sidewall spacers may be formed, upon which the metal etch can stop, leaving a metal line within the contact dimensions. A further alternative embodiment uses a conductive etch stop layer which covers the entire contact, and upon which the metal etch can stop within the contact opening.

摘要翻译： 公开了一种用于形成用于与集成电路中的导电元件接触的铝金属化的方法和根据该集成电路形成的集成电路。 根据第一个公开的实施例，第一铝合金层形成在触点内，可选地在其与下面的电极之间具有阻挡层。 在其上形成有对铝蚀刻剂物质具有低蚀刻速率的材料的蚀刻停止层。 在其上形成第二较厚的铝合金层。 蚀刻第二铝层直到达到蚀刻停止层; 用于限定金属线的掩模可以具有在接触开口的尺寸内的边缘。 在去除暴露的蚀刻停止层之后，定时蚀刻除去第一铝合金层，而不暴露触点的底部。 因此，金属线可以安全地形成，而不需要围绕接触开口的外壳。 根据替代实施例，可以形成导电或半导体侧壁间隔物，金属蚀刻可在其上停止，在接触尺寸内留下金属线。 另一替代实施例使用覆盖整个触点的导电蚀刻停止层，并且金属蚀刻可以在其上在接触开口内停止。

公开(公告)号：US5256895A

公开(公告)日：1993-10-26

申请号：US863519

申请日：1992-03-31

申请人： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

发明人： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L27/12 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/32 ,  H01L21/76205

摘要： Field oxide regions are formed between drive regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

摘要翻译： 通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的驱动区之间的场氧化物区域，打开这些层以暴露硅衬底的一部分，去除暴露的衬底的一层， 在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间​​的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。 在如图1所示的那些场地氧化物埋在衬底中的那些结构中。 如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

公开(公告)号：US5246883A

公开(公告)日：1993-09-21

申请号：US832088

申请日：1992-02-06

申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

摘要： A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

公开(公告)号：US5234852A

公开(公告)日：1993-08-10

申请号：US860112

申请日：1992-03-30

申请人： Fu-Tai Liou

发明人： Fu-Tai Liou

IPC分类号： H01L21/266 ,  H01L21/336

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L29/6659 ,  Y10S148/133

摘要： A method for forming field effect devices having lightly doped drain regions requires only a single dope and implant step. After patterning of the polycrystalline silicon gates, sloped sidewall spacers are formed alongside the gates. These spacers have a relatively linear slope from the top corners of the polycrystalline silicon gates to the substrate. A single implant of dopant results in heavily doped regions beyond the sidewall spacers with more lightly, and shallowly, doped regions next to the channel.

摘要翻译： 用于形成具有轻掺杂漏极区域的场效应器件的方法仅需要单个掺杂和注入步骤。 在多晶硅栅极图形化之后，沿着栅极形成倾斜的侧壁间隔物。 这些间隔物从多晶硅栅极的顶角到衬底具有相对线性的斜率。 单个掺杂剂的注入导致超过侧壁间隔物的重掺杂区域，在沟道旁边具有更轻的和浅的掺杂区域。

公开(公告)号：US5130268A

公开(公告)日：1992-07-14

申请号：US681080

申请日：1991-04-05

申请人： Fu-Tai Liou ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Fusen E. Chen

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76227

摘要： A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

公开(公告)号：US08629519B2

公开(公告)日：2014-01-14

申请号：US13333951

申请日：2011-12-21

申请人： Chien-Min Lee ,  Kuang-Ching Chen ,  Fu-Tai Liou

发明人： Chien-Min Lee ,  Kuang-Ching Chen ,  Fu-Tai Liou

IPC分类号： H01L29/82

CPC分类号： H01L43/02 ,  G01R33/098 ,  H01F10/3254 ,  H01L27/22

摘要： A tunneling magnetoresistance sensor including a substrate, an insulating layer, a tunneling magnetoresistance component and an electrode array is provided. The insulating layer is disposed on the substrate. The tunneling magnetoresistance component is embedded in the insulating layer. The electrode array is formed in a single metal layer and disposed in the insulating layer either below or above the TMR component. The electrode array includes a number of separate electrodes. The electrodes are electrically connected to the tunneling magnetoresistance component to form a current-in-plane tunneling conduction mode. The tunneling magnetoresistance sensor in this configuration can be manufactured with a reduced cost and maintain the high performance at the same time.

摘要翻译： 提供了包括基板，绝缘层，隧道磁阻部件和电极阵列的隧道式磁阻传感器。 绝缘层设置在基板上。 隧道磁阻分量嵌入在绝缘层中。 电极阵列形成在单个金属层中，并且设置在TMR部件的下方或上方的绝缘层中。 电极阵列包括多个单独的电极。 电极电连接到隧道磁阻分量以形成电流 - 平面隧穿传导模式。 这种结构中的隧道磁阻传感器可以以降低的成本制造并且同时保持高性能。