公开(公告)号：US08883020B2

公开(公告)日：2014-11-11

申请号：US13754170

申请日：2013-01-30

Applicant: Globalfoundries, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: B44C1/22 ,  H05K3/00

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。

公开(公告)号：US20140264479A1

公开(公告)日：2014-09-18

申请号：US13797001

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/40 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

Abstract translation: 一种方法包括在栅极结构附近形成侧壁间隔物，在侧壁间隔物上形成第一衬里层，在第一衬里层上形成第二衬里层，在衬底上方形成第一绝缘材料层并邻近第二衬层， 选择性地去除所述第二衬层的至少部分相对于所述第一衬层，在所述第一绝缘材料层之上形成第二绝缘材料层，执行至少一个第二蚀刻工艺以移除所述第一层和所述第二层的至少一部分 的绝缘材料和第一衬里层的至少部分，从而暴露侧壁间隔件的外表面，并且形成接触暴露的侧壁间隔物的外表面和晶体管的源极/漏极区域的导电接触。

公开(公告)号：US20140252424A1

公开(公告)日：2014-09-11

申请号：US13785403

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  John A. Iacoponi

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract translation: 一种方法公开了进行蚀刻工艺以在源极/漏极区域的至少一部分上方的绝缘材料层中形成接触开口，其中在蚀刻工艺完成之后，晶体管的栅极结构的一部分是 暴露的，在暴露的栅极结构上选择性地形成可氧化材料，将可氧化材料的至少一部分转化为氧化物材料，以及在导电耦合到源/漏区的接触开口中形成导电接触。 本文公开的新型晶体管器件包括位于晶体管的导电接触和栅极结构之间的氧化物材料，其中氧化物材料接触导电接触并接触栅极结构的外表面的一部分但不全部接触。

公开(公告)号：US08809920B2

公开(公告)日：2014-08-19

申请号：US13670674

申请日：2012-11-07

Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/76

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US20140138779A1

公开(公告)日：2014-05-22

申请号：US13682331

申请日：2012-11-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

公开(公告)号：US20140084383A1

公开(公告)日：2014-03-27

申请号：US13628914

申请日：2012-09-27

Applicant: GLOBALFOUNDRIES INC,

Inventor： Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/283 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/7624 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.

Abstract translation: 本文公开的一种说明性方法包括在鳍片上形成牺牲栅极结构，其中牺牲栅极结构包括牺牲栅极绝缘层，绝缘材料层，牺牲栅电极层和栅极盖层，形成侧壁间隔物 牺牲栅极结构的相邻相对侧，去除牺牲栅极结构，从而限定露出翅片的一部分的栅极腔，并在栅极腔中形成替换栅极结构。 本文公开的一个示例性器件包括由形成在衬底中的沟槽分开的多个翅片结构，位于沟槽内的局部隔离材料，位于鳍结构的部分周围并位于局部隔离材料之上的栅结构，以及蚀刻 停止层位于沟槽内的栅极结构和局部隔离材料之间。

公开(公告)号：US10734499B2

公开(公告)日：2020-08-04

申请号：US15986031

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

公开(公告)号：US10446665B2

公开(公告)日：2019-10-15

申请号：US15904982

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ying Hao Hsieh

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/165

Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

公开(公告)号：US10355086B2

公开(公告)日：2019-07-16

申请号：US15181843

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US20190206868A1

公开(公告)日：2019-07-04

申请号：US16294117

申请日：2019-03-06

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/033 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.