公开(公告)号：US09583628B2

公开(公告)日：2017-02-28

申请号：US14558904

申请日：2014-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Douglas C. La Tulipe, Jr.

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/772 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/78603 ,  H01L29/0847 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78654

Abstract: A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.

Abstract translation: 一种器件包括半导体衬底。 半导体衬底上的栅极叠层包括栅极介电层和栅极导体层。 低k间隔物与栅介质层相邻。 升高的源极/漏极（RSD）区域与低k间隔物相邻。 低k间隔物嵌入在RSD区域上的ILD中。

公开(公告)号：US09564486B2

公开(公告)日：2017-02-07

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US09466567B2

公开(公告)日：2016-10-11

申请号：US14957842

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/11 ,  H01L23/525 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L23/62

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

公开(公告)号：US09378948B2

公开(公告)日：2016-06-28

申请号：US14672157

申请日：2015-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L21/02532 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.

公开(公告)号：US09318580B2

公开(公告)日：2016-04-19

申请号：US14590327

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02494 ,  H01L21/02587 ,  H01L29/7853

Abstract: A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material.

Abstract translation: 形成U型半导体器件的方法包括沿形成在晶体层中的沟槽的侧壁和底部生长U形半导体材料。 U型半导体材料被锚固，并且去除晶体层。 在具有用于支撑的电介质材料的U形半导体材料下形成回填。 半导体器件由U形半导体材料形成。

公开(公告)号：US09219078B2

公开(公告)日：2015-12-22

申请号：US13865795

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

公开(公告)号：US09214397B2

公开(公告)日：2015-12-15

申请号：US13788689

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kerber ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Abstract translation: 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

公开(公告)号：US20150137308A1

公开(公告)日：2015-05-21

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.