公开(公告)号：US20160300754A1

公开(公告)日：2016-10-13

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针迹。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US20160093704A1

公开(公告)日：2016-03-31

申请号：US14963789

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

公开(公告)号：US09293462B2

公开(公告)日：2016-03-22

申请号：US14167778

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/4763 ,  H01L27/092 ,  H01L21/311 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/167 ,  H01L29/161

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有所选择的源极/漏极区域和未选择的源极/漏极区域的半导体衬底。 该方法在选定的源极/漏极区域上形成接触电阻调制材料。 此外，该方法在所选择的和非选择的源/漏区上形成金属层。 该方法包括退火金属层以在所选择的和非选择的源/漏区上形成硅化物接触。

公开(公告)号：US20160056104A1

公开(公告)日：2016-02-25

申请号：US14463803

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract translation: 本发明的实施例提供了一种在线结构的后端中自对准金属切割的方法。 牺牲Mx + 1线形成在金属Mx线之上。 每个Mx + 1牺牲线上形成间隔。 使用间隔件之间的间隙来确定切割到Mx金属线的位置和厚度。 这样可确保Mx金属线切割不会侵入连接Mx和Mx + 1电平的通孔。 它还允许通过外壳规则降低限制，从而增加电路密度。

公开(公告)号：US20160056075A1

公开(公告)日：2016-02-25

申请号：US14463801

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

Abstract translation: 本发明的实施例提供了一种在线结构后端切割牺牲金属线的方法。 牺牲Mx + 1线形成在金属Mx线之上。 在牺牲Mx + 1线上沉积并图案化切割光刻叠层并形成切割腔。 切割腔填充有介电材料。 选择性蚀刻工艺去除牺牲Mx + 1线，保留填充切割腔的电介质。 然后通过沉积除去牺牲Mx + 1线的金属形成预切割的金属线。 因此，本发明的实施例提供预切割金属线，并且不需要金属切割。 通过避免金属切割的需要，避免与金属切割相关的风险。

公开(公告)号：US20160049489A1

公开(公告)日：2016-02-18

申请号：US14457934

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jing Wan ,  Guillaume Bouche ,  Andy Wei ,  Shao Ming Koh

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract translation: 提供了集成电路及其制造方法。 一种集成电路的制造方法，其特征在于，形成覆盖基板的分层散热片，其中层状散热片包括SiGe层和Si层。 SiGe层和Si层沿层状翅片的高度交替。 形成覆盖基板和分层翅片的虚拟栅极以及与层状翅片接触形成的源极和漏极区域。 去除伪栅极以暴露SiGe层和Si层，并且去除Si层以产生SiGe纳米线。 形成在源极和漏极之间封装SiGe纳米线的高K电介质层，并且形成替代金属栅极，使得替代金属栅极包围源极和漏极之间的高K电介质层和SiGe纳米线。

公开(公告)号：US20150380250A1

公开(公告)日：2015-12-31

申请号：US14318901

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Gabriel Padron Wells ,  Xiang Hu

IPC: H01L21/28 ,  H01L21/762 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/28008 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.

Abstract translation: 本发明的实施例提供了改进的接触形成的结构和方法。 在与翅片间隔开的区域中，从栅极去除顶盖氮化物。 这有助于减少处理步骤，允许栅极和源极/漏极区域以相同的工艺步骤打开。 可以使用极紫外光刻（EUVL）来形成抗蚀剂以形成接触。

公开(公告)号：US09224638B2

公开(公告)日：2015-12-29

申请号：US14275448

申请日：2014-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Kisik Choi ,  Hoon Kim ,  Andy Wei ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

Abstract translation: 提供了用金属 - 氧化钛触点形成半导体器件的器件和方法。 一个中间半导体器件包括例如：衬底，设置在衬底上的至少一个场效应晶体管，位于至少一个场效应晶体管的至少第一部分之间的第一接触区域，位于间隔物和中间层之间 电介质和位于至少一个场效应晶体管的至少一个第二部分之间的第二接触区域在间隔物和层间电介质之间。 一种方法包括例如获得中间半导体器件并在中间半导体器件上形成至少一个接触。

公开(公告)号：US20150340467A1

公开(公告)日：2015-11-26

申请号：US14282089

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Abstract translation: 提供了在半导体器件中形成合并的栅极和源极/漏极（S / D）触点的方法。 具体地，一种方法提供了在衬底上形成的一组栅极结构上的介电层; 在栅极结构之间的电介质层中图案化的一组源/漏（S / D）开口; 形成在栅极结构之上的填充材料，包括在S / D开口内; 以及在栅极结构上图案化的一组栅极开口，其中除去形成在S / D开口之一内的与填充材料直接相邻的电介质层的一部分。 然后去除填充材料，对电介质层有选择性，并且在半导体器件上沉积金属材料以在栅极开口内形成一组栅极触点，以及S / D开口内的一组S / D触点， 其中一个栅极触点和一个S / D触点被合并。

公开(公告)号：US20150311082A1

公开(公告)日：2015-10-29

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L21/28 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

Abstract translation: 提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地说，栅极接触开口形成在一组栅极结构中的至少一个上，在半导体器件的鳍片之上形成一组S / D接触开口，并且在半导体器件上沉积金属材料以形成栅极 在门接触开口内接触一组S / D接触开口内的一组S / D接点。 在一种方法中，氮化物保留在栅极接触和至少一个S / D接触之间。 在另一种方法中，该装置包括合并门和S / D触点。 这种方法提供对分隔区域的选择性蚀刻，其中氧化物将被进一步选择性地去除氮化物以产生空穴以金属化并产生与S / D的接触，而接触区域之间的隔离区域被氮化物包围并且在氧化物蚀刻期间不被去除 。