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    Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices
    42.
    发明授权
    Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices 有权

    公开(公告)号：US10529826B1

    公开(公告)日：2020-01-07

    申请号：US16101876

    申请日：2018-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

    IPC: H01L29/66 ,  H01L21/764 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

    Abstract: A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in the gate cavity, recessing the first dielectric layer and the sidewall spacer to expose sidewall surfaces of the cap layer, removing the inner spacer to define a first spacer cavity, forming an upper spacer in the spacer cavity and contacting sidewall surfaces of the cap layer, forming a second dielectric layer above the upper spacer and the cap layer, and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.

    Vertically stacked complementary-FET device with independent gate control
    43.
    发明授权
    Vertically stacked complementary-FET device with independent gate control 有权

    公开(公告)号：US10510622B1

    公开(公告)日：2019-12-17

    申请号：US16047456

    申请日：2018-07-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet Harischandra Suvarna

    IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

    Abstract: A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode.

    INNER SPACER FORMATION IN A NANOSHEET FIELD-EFFECT TRANSISTOR
    46.
    发明申请
    INNER SPACER FORMATION IN A NANOSHEET FIELD-EFFECT TRANSISTOR 审中-公开

    公开(公告)号：US20190058052A1

    公开(公告)日：2019-02-21

    申请号：US15680467

    申请日：2017-08-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/223 ,  H01L21/311

    Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a sacrificial layer arranged vertically between the first and second nanosheet channel layers. The sacrificial layer is laterally recessed at a sidewall of the body feature to expose respective portions of the first and second nanosheet channel layers. A sacrificial spacer is formed by oxidizing a portion of the sacrificial layer at the sidewall of the body feature. Sections of a semiconductor material are epitaxially grown on the exposed portions of the first and second nanosheet channel layers to narrow a gap vertically separating the first and second nanosheet channel layers. The sacrificial spacer is removed to form a cavity between the sections of the semiconductor material and the sacrificial layer. A dielectric spacer is conformally deposited in the cavity.

    ASYMMETRIC GATE CUT ISOLATION FOR SRAM
    49.
    发明申请
    ASYMMETRIC GATE CUT ISOLATION FOR SRAM 有权

    公开(公告)号：US20210020644A1

    公开(公告)日：2021-01-21

    申请号：US16515913

    申请日：2019-07-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

    IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238

    Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.

    Nanosheet field-effect transistors formed with sacrificial spacers
    50.
    发明授权
    Nanosheet field-effect transistors formed with sacrificial spacers 有权

    公开(公告)号：US10818792B2

    公开(公告)日：2020-10-27

    申请号：US16106291

    申请日：2018-08-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Daniel Chanemougame

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234

    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A layer stack includes nanosheet channel layers arranged to alternate with sacrificial layers. First and second gate structures are formed that extend across the layer stack and that are separated by a first gap. First and second sidewall spacers are formed over the layer stack and within the first gap respectively adjacent to the first and second gate structures, and the layer stack is subsequently etched to form first and second body features that are separated by a second gap. The sacrificial layers are recessed relative to the nanosheet channel layers to define indents in the first and second body features, and the first and second sidewall spacers are subsequently removed. After removing the first and second sidewall spacers, a conformal layer is deposited in the second gap that fills the indents to define inner spacers.

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