公开(公告)号：US09082876B2

公开(公告)日：2015-07-14

申请号：US13842103

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/38 ,  H01L21/8238 ,  H01L21/266

CPC classification number: H01L21/823807 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在制造集成电路的方法的实施例中，在半导体衬底上形成P型栅电极结构和N型栅电极结构。 栅电极结构各自包括覆盖在栅极电介质层上的栅电极和覆盖在栅电极上的氮化物盖。 使用P型栅极电极结构和N型栅极电极结构作为掩模将电导率确定离子注入到半导体衬底中，以形成用于P型栅电极结构和N型栅极的源极区和漏极区 电极结构。 在将导电性确定离子注入半导体衬底期间，氮化物盖保持覆盖在N型栅电极结构上，以形成用于N型栅电极结构的源区和漏区。

公开(公告)号：US09076815B2

公开(公告)日：2015-07-07

申请号：US13907362

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/266 ,  H01L21/8238

CPC classification number: H01L29/6653 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract translation: 制造晶体管时的已知问题是由间隔物不期望地引入晶体管沟道区域的应力。 为了解决这个问题，本发明提出了一种旨在缓和间隔物材料的应力的离子注入。 在间隔件已经完全形成之后进行松弛植入。 松弛植入可以在硅化处理之后或在源极和漏极区域中的注入步骤之后进行激活退火并且在进行硅化处理之前进行。

公开(公告)号：US20150102426A1

公开(公告)日：2015-04-16

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US20140246698A1

公开(公告)日：2014-09-04

申请号：US13783517

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract translation: 当形成复杂的P沟道晶体管时，在包括晶体管有源区的半导体层的表面上形成半导体合金层。 当与该半导体合金层邻接形成金属硅化物层时，观察到金属硅化物层与分离的团簇的聚集。 为了解决这个问题，本发明提出一种方法和半导体器件，其中在形成金属硅化物层之前去除位于晶体管的源极和漏极区域上的半导体合金层的部分。 以这种方式，金属硅化物层形成为与半导体层邻接，而不形成为半导体合金层。

公开(公告)号：US10340380B2

公开(公告)日：2019-07-02

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/161

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

公开(公告)号：US10176859B2

公开(公告)日：2019-01-08

申请号：US15585709

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Duenkel ,  Ralf Illgen ,  Ralf Richter ,  Soeren Jansen

IPC: G11C16/24 ,  G11C11/22 ,  H01L29/78 ,  G11C16/04 ,  G11C16/06

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

公开(公告)号：US10033383B1

公开(公告)日：2018-07-24

申请号：US15463316

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Duenkel ,  Sven Beyer

IPC: H03K19/00 ,  H03K19/0185 ,  H01L29/78

Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

公开(公告)号：US20180158835A1

公开(公告)日：2018-06-07

申请号：US15366425

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Thomas Melde ,  Elke Erben

IPC: H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11573 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/0332 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/518

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

公开(公告)号：US09842845B1

公开(公告)日：2017-12-12

申请号：US15337441

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Melde ,  Ralf Richter

IPC: H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/31111 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present disclosure provides a semiconductor device structure including a non-volatile memory (NVM) device structure in and above a first region of a semiconductor substrate and a logic device formed in and above a second region of the semiconductor substrate different from the first region. The NVM device structure includes a floating-gate, a first select gate and at least one control gate. The logic device includes a logic gate disposed on the second region and source/drain regions provided in the second region adjacent to the logic gate. The control gate extends over the floating-gate and the first select gate is laterally separated from the floating-gate by an insulating material layer portion. Upon forming the semiconductor device structure, the floating gate is formed before forming the control gate and the logic device.

公开(公告)号：US09754951B2

公开(公告)日：2017-09-05

申请号：US14982228

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer

IPC: H01L27/115 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/423 ,  H01L27/11521 ,  H01L21/762

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/0649 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.