公开(公告)号：US11004748B2

公开(公告)日：2021-05-11

申请号：US16432899

申请日：2019-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L27/088

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

公开(公告)号：US10971625B2

公开(公告)日：2021-04-06

申请号：US16458178

申请日：2019-06-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Michael V Aquilino ,  Daniel Jaeger ,  Man Gu ,  Bradley Morgenfeld ,  Haiting Wang ,  Kavya Sree Duggimpudi ,  Wang Zheng

IPC: H01L29/08 ,  H01L27/112 ,  H01L29/78 ,  H01L21/822 ,  H01L29/66

Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

公开(公告)号：US12107154B2

公开(公告)日：2024-10-01

申请号：US18324489

申请日：2023-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/7851

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US11908917B2

公开(公告)日：2024-02-20

申请号：US17404499

申请日：2021-08-17

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4983 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/66795

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

公开(公告)号：US11812670B2

公开(公告)日：2023-11-07

申请号：US18052307

申请日：2022-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H10N50/80 ,  H10B51/30 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10B51/30 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/011 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/881

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

公开(公告)号：US11652142B2

公开(公告)日：2023-05-16

申请号：US17482374

申请日：2021-09-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mankyu Yang ,  Richard Taylor, III ,  Alexander Derrickson ,  Alexander Martin ,  Jagar Singh ,  Judson Robert Holt ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/10

CPC classification number: H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/735

Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.

公开(公告)号：US20230078730A1

公开(公告)日：2023-03-16

申请号：US18052307

申请日：2022-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L27/1159 ,  H01L43/08 ,  H01L45/00 ,  H01L43/12 ,  H01L43/10

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

公开(公告)号：US20230069207A1

公开(公告)日：2023-03-02

申请号：US17524043

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Judson R. Holt ,  Haiting Wang ,  Jagar Singh ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

公开(公告)号：US20230061156A1

公开(公告)日：2023-03-02

申请号：US17687741

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ali Razavieh ,  Jagar Singh ,  Haiting Wang

IPC: H01L29/735 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/73

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

公开(公告)号：US11502200B2

公开(公告)日：2022-11-15

申请号：US16906490

申请日：2020-06-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Judson R. Holt ,  Haiting Wang ,  Yanping Shen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: An illustrative transistor device disclosed herein includes a gate structure positioned around a portion of a fin defined in a semiconductor substrate and epitaxial semiconductor material positioned on the fin in a source/drain region of the transistor device, wherein the epitaxial semiconductor material has a plurality of lower angled surfaces. In this example, the device further includes a first sidewall spacer positioned adjacent the gate structure, wherein a first portion of the first sidewall spacer is also positioned on and in physical contact with at least a portion of the lower angled surfaces of the epitaxial semiconductor material.