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    ELECTROSTATIC DISCHARGE PROTECTION SYSTEM
    41.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION SYSTEM 有权
    静电放电保护系统

    公开(公告)号：US20150349522A1

    公开(公告)日：2015-12-03

    申请号：US14289083

    申请日：2014-05-28

    申请人： James W. Miller ,  Melanie Etherton ,  Alex P. Gerdemann ,  Mohamed S. Moosa ,  Jonathan M. Phillippe ,  Robert S. Ruth

    发明人： James W. Miller ,  Melanie Etherton ,  Alex P. Gerdemann ,  Mohamed S. Moosa ,  Jonathan M. Phillippe ,  Robert S. Ruth

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0248 ,  H01L24/06 ,  H01L27/0292 ,  H01L27/0296 ,  H02H3/20 ,  H02H9/04 ,  H02H9/046 ,  H05K9/006

    摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

    摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。

    Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET)
    42.
    发明授权
    Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET) 有权
    通过形成金属氧化物半导体场效应晶体管（MOSFET）来形成非易失性存储器（NVM）的栅极堆叠，

    公开(公告)号：US08426263B2

    公开(公告)日：2013-04-23

    申请号：US13077569

    申请日：2011-03-31

    申请人： Bradley P. Smith ,  James W. Miller

    发明人： Bradley P. Smith ,  James W. Miller

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

    摘要翻译： 在晶体管区域和NVM区域的基板上形成第一电介质层，在第一电介质层上形成第一导电层，在第一导电层上形成第二电介质层，在第一导电层上形成第二导电层 第二电介质层。 执行图案化蚀刻以去除晶体管区域中的第二导电层的至少一部分并且暴露第一导电层的延伸部分。 在具有第一图案的晶体管区域上形成第一掩模，其中第一图案是MOSFET的栅极堆叠，以及在延伸部分中从栅极堆叠延伸的延伸部分，以及位于NVM区域上的第二掩模，其具有第二图案 图案，其中所述第二图案是所述NVM单元的栅极堆叠。 然后执行图案化蚀刻。

    PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)
    43.
    发明申请
    PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 有权
    形成金属氧化物半导体场效应晶体管（MOSFET）的非易失性存储器（NVM）的栅极堆栈

    公开(公告)号：US20120252179A1

    公开(公告)日：2012-10-04

    申请号：US13077569

    申请日：2011-03-31

    申请人： Bradley P. Smith ,  James W. Miller

    发明人： Bradley P. Smith ,  James W. Miller

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

    摘要翻译： 在晶体管区域和NVM区域的基板上形成第一电介质层，在第一电介质层上形成第一导电层，在第一导电层上形成第二电介质层，在第一导电层上形成第二导电层 第二电介质层。 执行图案化蚀刻以去除晶体管区域中的第二导电层的至少一部分并且暴露第一导电层的延伸部分。 在具有第一图案的晶体管区域上形成第一掩模，其中第一图案是MOSFET的栅极堆叠，并且在从栅极堆叠延伸的延伸部分中的延伸部分以及在NVM区域上的第二掩模，其具有第二图案 图案，其中所述第二图案是所述NVM单元的栅极堆叠。 然后执行图案化蚀刻。

    Distributed electrostatic discharge protection circuit with varying clamp size
    44.
    发明授权
    Distributed electrostatic discharge protection circuit with varying clamp size 有权
    具有不同钳位尺寸的分布式静电放电保护电路

    公开(公告)号：US07589945B2

    公开(公告)日：2009-09-15

    申请号：US11513638

    申请日：2006-08-31

    申请人： James W. Miller ,  Melanie Etherton ,  Michael G. Khazhinsky ,  Michael Stockinger

    发明人： James W. Miller ,  Melanie Etherton ,  Michael G. Khazhinsky ,  Michael Stockinger

    IPC分类号： H02H9/00

    CPC分类号： H02H9/046 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.

    摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。

    TORSION BLADE PIVOT WINDMILL
    45.
    发明申请
    TORSION BLADE PIVOT WINDMILL 审中-公开

    公开(公告)号：US20090191058A1

    公开(公告)日：2009-07-30

    申请号：US12271235

    申请日：2008-11-14

    申请人： James W. Miller

    发明人： James W. Miller

    IPC分类号： F03D1/06

    CPC分类号： F03D1/0658 ,  F03D1/0608 ,  F05B2240/30 ,  Y02E10/721 ,  Y02E10/726

    摘要： A pair of airfoil blades having a longitudinal axis coincident with one another. Each blade is bent at the center on the plane of the chord. Each blade has an airfoil tip blade placed at the outer most trailing edge. The blades are affixed by their root ends to opposite ends of a torsion shaft. The blade chords are offset from one another, which defines a blade pitch angle. The torsion shaft is journaled perpendicular through a driveshaft, whereas the rotation of the blades can transfer through the torsion shaft to the driveshaft and cause the driveshaft to turn, eliminating the need for a hub. The blades are adapted to pivot along with the torsion shaft. The blades lie in substantially the same plane, and are adapted for rotation in a plane orthogonal to the longitudinal axis of the driveshaft. Each blade has an airfoil shaped fluid gate valve disposed on the leading edge.

    摘要翻译： 一对具有彼此重合的纵轴的翼型叶片。 每个叶片在和弦平面上的中心弯曲。 每个叶片具有放置在最外侧最后缘的翼型末端叶片。 叶片的根端固定在扭转轴的相对端。 叶片和弦彼此偏移，这限定了叶片桨距角。 扭转轴通过驱动轴垂直地轴向旋转，而叶片的旋转可以通过扭转轴传递到驱动轴，并使驱动轴转动，从而无需轮毂。 叶片适于与扭转轴一起枢转。 叶片位于基本上相同的平面中，并且适于在与驱动轴的纵向轴线正交的平面中旋转。 每个叶片具有设置在前缘上的翼型流体闸阀。

    Adjustable strap for a person to carry a heavy load
    47.
    发明授权
    Adjustable strap for a person to carry a heavy load 失效
    可调节的皮带为人承担沉重的负担

    公开(公告)号：US07390042B1

    公开(公告)日：2008-06-24

    申请号：US11154069

    申请日：2005-06-16

    申请人： James W. Miller

    发明人： James W. Miller

    IPC分类号： B65G7/12

    CPC分类号： B65G7/12

    摘要： A strap includes an adjusting buckle near each end and a handle on each end. The length of the strap is adjusted using the buckles so a heavy load can be handled by a worker in a manner that permits the worker to safely carry the load in a variety of situations.

    摘要翻译： 表带包括在每个端部附近的调节带扣和每端的手柄。 使用带扣调节带子的长度，使得工人可以以允许工人在各种情况下安全地承载负载的方式来处理重负荷。

    Electrostatic discharge protection circuitry and method of operation
    49.
    发明授权
    Electrostatic discharge protection circuitry and method of operation 有权
    静电放电保护电路及操作方法

    公开(公告)号：US06724603B2

    公开(公告)日：2004-04-20

    申请号：US10216336

    申请日：2002-08-09

    申请人： James W. Miller ,  Geoffrey B. Hall ,  Alexander Krasin ,  Michael Stockinger ,  Matthew D Akers ,  Vishnu G. Kamat

    发明人： James W. Miller ,  Geoffrey B. Hall ,  Alexander Krasin ,  Michael Stockinger ,  Matthew D Akers ,  Vishnu G. Kamat

    IPC分类号： H02H322

    CPC分类号： H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.

    摘要翻译： 静电放电（ESD）保护电路（9）包括多个I / O和电源焊盘单元（22,40），其包括外部焊盘（31,41）和需要ESD保护的电路。 保护电路包括并联在ESD总线（14）和VSS总线（18）之间并分布在多个焊盘单元之间的分流器件阵列（36,46）。 一个或多个触发电路（50）控制分流装置。 ESD事件从任何应力焊盘耦合到两个单独的总线上：将高ESD电流路由到多个分流装置的正电流电极的ESD总线以及控制触发电路的升压总线（12）。 在ESD事件期间，触发电路将分流装置的控制电极驱动到比现有技术电路更可能的电压电平，从而降低分流装置的导通电阻。

    Method for forming a well under isolation and structure thereof
    50.
    发明授权
    Method for forming a well under isolation and structure thereof 失效
    用于在隔离下形成井的方法及其结构

    公开(公告)号：US06500723B1

    公开(公告)日：2002-12-31

    申请号：US09972397

    申请日：2001-10-05

    申请人： Michael G. Khazhinsky ,  Aykut Dengi ,  James W. Miller

    发明人： Michael G. Khazhinsky ,  Aykut Dengi ,  James W. Miller

    IPC分类号： H01L2120

    CPC分类号： H01L28/20 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/74 ,  H01L27/0288 ,  H01L27/0802 ,  Y10S438/947

    摘要： A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

    摘要翻译： 使用与用于常规孔的光致抗蚀剂和植入步骤相同的掩模形成隔离层下面的许多小孔。 小孔形成得足够接近，使得它们在正常的后续半导体处理期间合并以形成合并井。 正常井和小井的浓度大于合并井的浓度。 通过确保小井足够靠近，使得从正在使用的特定半导体工艺发生的井注入的正常扩散导致合并，确保小井的期望合并。 与掺杂浓度较低的合并井的一个理想用途是作为电阻器，具有比常规阱更多的电阻，而不需要额外的注入。