公开(公告)号：US07598100B2

公开(公告)日：2009-10-06

申请号：US11719112

申请日：2004-11-18

申请人： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

发明人： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC分类号： H01L21/00 ,  H01L31/26 ,  H01L21/66 ,  H01L21/82

CPC分类号： G01R1/0735 ,  G01R3/00

摘要： As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

摘要翻译： 随着用于防止多层布线基板1翘曲的卡夹的厚度增加，存在薄膜片2被埋在卡夹中并且不能实现探针7和测试垫之间的牢固接触的​​问题。 为了防止，薄膜片2和接合环6在仅向薄膜片2的中心区域IA施加张力的状态下接合，并且拉伸力不施加到外围区域 OA。 然后，限定高达薄膜片2的探针表面的高度的接合环6的高度增加，从而增加高达薄膜片2的探针表面的高度。

公开(公告)号：US07537943B2

公开(公告)日：2009-05-26

申请号：US11866301

申请日：2007-10-02

申请人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

发明人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

摘要翻译： 提供一种制造半导体集成电路器件的技术，用于在使用由该制造技术形成的膜探针进行探针检查时，减少将异物附着于膜探针的可能性。 用于挤压薄膜片的按压部件包括相对设置在上侧的压接销接收部，用于接收凹部中的柱塞的按压销的前端，以及相对设置在下方的膜片按压部。 与膜片接触的膜片按压部具有最小的平面尺寸，能够对要进行探头检查的一个感兴趣的芯片的整个表面进行按压。

公开(公告)号：US20090017565A1

公开(公告)日：2009-01-15

申请号：US11816369

申请日：2005-03-11

申请人： Akio Hasebe ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Naoki Okamoto

发明人： Akio Hasebe ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Naoki Okamoto

IPC分类号： H01L21/66

CPC分类号： H01L24/10 ,  G01R31/2889 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014

摘要： A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

摘要翻译： 在探针测试时，探针与测试垫接触，而不会破坏芯片中形成的电路。 因此，通过用螺母和螺栓固定，将装载夹具，压制工具，弹性体，粘合环和柱塞制成一体。 安装在弹簧保持夹具和负载夹具之间的弹簧的弹力用于使得用作这些弹簧的构件可以朝向垫PD压下。 从弹簧传递到柱塞到薄膜片的推力仅用于薄膜片的延伸。

公开(公告)号：US20080096295A1

公开(公告)日：2008-04-24

申请号：US11866301

申请日：2007-10-02

申请人： Akio HASEBE ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

发明人： Akio HASEBE ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

摘要翻译： 提供一种制造半导体集成电路器件的技术，用于在使用由该制造技术形成的膜探针进行探针检查时，减少将异物附着于膜探针的可能性。 用于挤压薄膜片的按压部件包括相对设置在上侧的压接销接收部，用于接收凹部中的柱塞的按压销的前端，以及相对设置在下方的膜片按压部。 与膜片接触的膜片按压部具有最小的平面尺寸，能够对要进行探头检查的一个感兴趣的芯片的整个表面进行按压。

公开(公告)号：US20060281222A1

公开(公告)日：2006-12-14

申请号：US11448071

申请日：2006-06-07

申请人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka

发明人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC分类号： H01L21/00

CPC分类号： G01R1/0735

摘要： By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

公开(公告)号：US20060091553A1

公开(公告)日：2006-05-04

申请号：US11302582

申请日：2005-12-13

申请人： Yasunori Narizuka ,  Mitsuko Itou ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei

发明人： Yasunori Narizuka ,  Mitsuko Itou ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei

IPC分类号： H01L23/48

CPC分类号： H05K3/3463 ,  H01L21/4853 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0949 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00014

摘要： The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

公开(公告)号：US5320729A

公开(公告)日：1994-06-14

申请号：US914469

申请日：1992-07-17

申请人： Yasunori Narizuka ,  Masakazu Ishino ,  Akihiro Kenmotsu ,  Yoshitaka Chiba ,  Akitoshi Hiraki

发明人： Yasunori Narizuka ,  Masakazu Ishino ,  Akihiro Kenmotsu ,  Yoshitaka Chiba ,  Akitoshi Hiraki

IPC分类号： C23C14/34

CPC分类号： H01J37/3426 ,  H01J37/3491

摘要： Disclosed herein is a sputtering target with which a high resistivity thin film consisting of chromium, silicon and oxygen can be produced economically and stably for a long time. Also disclosed is a process for producing the sputtering target by selecting the grain size of a chromium (Cr) powder and a silicon dioxide (SiO.sub.2) powder, drying the powders sufficiently by heating, then mixing the dried powders to obtain a mixed powder containing generally from 20 to 80% by weight of chromium, most preferably from 50 to 80% by weight of chromium, the remainder being silicon dioxide, packing the mixed powder in a die, and sintering the packed powder by hot pressing or the like, to produce a desired sputtering target which has a two phase mixed structure. The sputtering target can be used for manufacture of thin film resistors and electric circuits.

摘要翻译： 本文公开了一种溅射靶，其可以经济地且稳定地长时间生产由铬，硅和氧组成的高电阻率薄膜。 还公开了通过选择铬（Cr）粉末和二氧化硅（SiO 2）粉末的晶粒尺寸来制造溅射靶的方法，通过加热将粉末充分干燥，然后混合干燥粉末，得到通常含有的混合粉末 20至80重量％的铬，最优选为50至80重量％的铬，其余为二氧化硅，将混合粉末包装在模具中，并通过热压等烧结填充的粉末，以产生 具有两相混合结构的期望的溅射靶。 溅射靶可用于薄膜电阻和电路的制造。