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    Parallel computer system and parallel computing method
    43.
    发明授权
    Parallel computer system and parallel computing method 失效
    并行计算机系统和并行计算方法

    公开(公告)号：US06631391B1

    公开(公告)日：2003-10-07

    申请号：US09544359

    申请日：2000-04-06

    申请人： Shinjiro Inabata ,  So Yamada ,  Nobuaki Miyakawa ,  Takashi Amisaki ,  Hajime Takashima ,  Kunihiro Kitamura

    发明人： Shinjiro Inabata ,  So Yamada ,  Nobuaki Miyakawa ,  Takashi Amisaki ,  Hajime Takashima ,  Kunihiro Kitamura

    IPC分类号： G06F738

    CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/3885

    摘要： There is provided a parallel computer and a parallel computing method which allows high precision parallel calculation to be executed without requiring a hardware scale while maintaining high calculation speed. A system is constructed by connecting a host processor with a plurality of special purpose processors via buses. The host processor carries out the operation in a format of double-precision floating-point and the special purpose processor carries out the operation in an internal format of floating-point. The special purpose processor comprises an input data converting section for converting from the double-precision to the internal format and an output data converting section for converting from the internal format to the double-precision. Because the sign part and the exponent part can use data in common in the data before and after the conversion, only the mantissa part is converted by a specific procedure.

    摘要翻译： 提供了并行计算机和并行计算方法，其允许执行高精度并行计算，而不需要硬件规模，同时保持高的计算速度。 通过总线将主机处理器与多个专用处理器连接构成系统。 主机处理器以双精度浮点格式进行操作，专用处理器以浮点的内部格式进行操作。 专用处理器包括用于从双精度转换为内部格式的输入数据转换部分和用于从内部格式转换为双精度的输出数据转换部分。 因为符号部分和指数部分可以在转换之前和之后的数据中使用共同的数据，所以仅通过特定过程转换尾数部分。

    Floating-point accumulator
    44.
    发明授权
    Floating-point accumulator 失效
    浮点累加器

    公开(公告)号：US6073155A

    公开(公告)日：2000-06-06

    申请号：US901671

    申请日：1997-07-28

    申请人： Shinjiro Inabata ,  So Yamada ,  Shinjiro Toyoda ,  Nobuaki Miyakawa

    发明人： Shinjiro Inabata ,  So Yamada ,  Shinjiro Toyoda ,  Nobuaki Miyakawa

    IPC分类号： G06F7/485 ,  G06F7/50 ,  G06F17/10 ,  G06F7/38

    CPC分类号： G06F7/485

    摘要： To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows:When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.

    摘要翻译： 为了获得足够精确的浮点积累结果，即使计算量很大，根据本发明的浮点累加器如下构成：当两个浮点数据存储在任何移位寄存器中时， 两个数据分别通过连接到缓冲器移位寄存器的一个BUS0和BUS1输出。 两个输出数据通过BUS0和BUS1输入加法器，并在添加浮点数后作为相加结果数据输出。 上述相加的结果数据通过BUSW和多路复用器返回到移位寄存器的每个输入，并且在相加之前通过移位寄存器保持浮点数据之一来写入与移位寄存器相对应的移位寄存器。 通过重复上述操作来累积浮点数。

    High speed readout circuit
    45.
    发明授权
    High speed readout circuit 失效
    高速读出电路

    公开(公告)号：US5204838A

    公开(公告)日：1993-04-20

    申请号：US751618

    申请日：1991-08-21

    申请人： Jinshu Son ,  Nobuaki Miyakawa

    发明人： Jinshu Son ,  Nobuaki Miyakawa

    IPC分类号： G11C7/06 ,  G11C16/26 ,  H03K5/02 ,  H03K5/24

    CPC分类号： G11C16/26 ,  G11C7/06 ,  G11C7/067 ,  H03K5/023 ,  H03K5/249

    摘要： The high speed readout circuit has an amplifier unit and an operating point setting unit and reads data from a memory sense line at high speed. The circuit further includes a unit for setting an operating point of the amplifier unit by short-circuiting the input and output terminals of the amplifier in response to a first control signal and precharging the sense line up to the operating point, and a unit for setting the sense line at a voltage slightly deviating the operating point in response to a second control signal by making use of a Miller capacitance and sensing the variations from the preset voltage during a reading process.

    摘要翻译： 高速读出电路具有放大器单元和工作点设定单元，并以高速从存储感测线读出数据。 该电路还包括一个单元，用于根据第一控制信号短路放大器的输入和输出端，并将感测线预充电到工作点来设置放大器单元的工作点，以及一个设置单元 通过利用米勒电容并在读取过程中感测来自预设电压的变化，响应于第二控制信号使电压稍微偏离工作点的感测线。

    Image-processing integrated circuit device
    47.
    发明授权
    Image-processing integrated circuit device 失效
    图像处理集成电路器件

    公开(公告)号：US5027423A

    公开(公告)日：1991-06-25

    申请号：US378543

    申请日：1989-07-12

    申请人： Tetsuro Kawata ,  Eiri Hashimoto ,  Nobuaki Miyakawa

    发明人： Tetsuro Kawata ,  Eiri Hashimoto ,  Nobuaki Miyakawa

    IPC分类号： H04N1/409 ,  G06T5/20 ,  H03H17/02

    CPC分类号： H03H17/0202

    摘要： An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.

    摘要翻译： 图像处理集成电路装置包括延迟电路和加法器组，乘法块组和加法器组。 窗口中的图像数据逐行地馈送到延迟电路和加法器组，然后对于窗口中的每个对称位置相加。 对于每个对称位置，这样相加的图像数据的各个和乘以乘法块组中的对应系数数据。 最后，由加法器组相加从乘积组获得的相乘乘法结果，从而获得滤波器输出。 延迟电路和加法器组，乘法块组和加法器组可以集成形成一个图像处理集成电路器件。 因此，部件的数量减少。 此外，不仅可以将图像数据同时馈送到延迟电路和加法器组，而且还可以并行地并行地通过使用为窗口中的对称位置提供的专用乘法块来执行乘法器组中的乘法。 因此，滤波处理的速度变高。

    Memory device with improved common data line bias arrangement
    48.
    发明授权
    Memory device with improved common data line bias arrangement 失效
    具有改进的公共数据线偏置布置的存储器件

    公开(公告)号：US4829479A

    公开(公告)日：1989-05-09

    申请号：US108623

    申请日：1987-10-15

    申请人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

    发明人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

    IPC分类号： G11C11/417 ,  G11C7/10

    CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

    摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

    摘要翻译： 一种存储器件，其中使用多个阻抗元件分压由最高工作电压下降固定电压的电压，并且公共数据线被分压电压偏置。 由于施加了来自最高工作电位的固定电压降低的电压，即使当阻抗元件的电阻值降低时，流过阻抗元件路径的电流也不会显着增加，并且获得低功耗 。 由于阻抗元件的电阻值降低，所以由寄生于公共数据线的电阻和杂散电容确定的时间常数减小。 因此，与存储在存储单元中的信息对应地产生的公用数据线的电位变化加快，数据检测时间缩短，可以缩短访问时间。

    Method for controlling an instrument panel display
    49.
    发明授权
    Method for controlling an instrument panel display 失效
    用于控制仪表板显示的方法

    公开(公告)号：US4404648A

    公开(公告)日：1983-09-13

    申请号：US56224

    申请日：1979-07-10

    申请人： Nobuaki Miyakawa ,  Masayuki Miki

    发明人： Nobuaki Miyakawa ,  Masayuki Miki

    IPC分类号： G05B23/02 ,  G01D5/244 ,  G01D7/00 ,  G01D7/02 ,  G01D7/04 ,  G01P3/48 ,  G01P3/489 ,  G01R31/00 ,  G01R31/28 ,  G06F3/147 ,  G06F9/46 ,  G06F17/40 ,  G09G3/00 ,  G09G3/20 ,  G06F3/14

    CPC分类号： G06F3/147 ,  G01D5/244 ,  G01D7/02 ,  G01P1/08 ,  G01R31/007 ,  G01R31/2834 ,  G09G2360/04

    摘要： In a system for displaying a plurality of parameters, such as on an instrument panel of a vehicle, a plurality of signals in the form of pulses each having a pulse frequency corresponding to a respective parameter are generated by respective sensors. Each pulse supplied from these signals to a status register results in generation of an interrupt request signal to a central processing unit. The central processing unit controls a mask register which in turn controls a gating arrangement which selectively masks or inhibits the application of pulses from one or more sensors to the status register so that upon receiving a first interrupt request signal, the central processing unit can mask all sensors but the one responsible for the interrupt request signal and proceed with calculation of the parameter associated therewith by measuring the interval between subsequently-generated interrupt request signals, such measurement being carried out by execution of increment instructions. Internal timing and the use of flags provides for the calculation of successive values of different parameters and the periodic display thereof.

    摘要翻译： 在用于显示多个参数的系统中，例如在车辆的仪表板上，通过相应的传感器产生各自具有对应于相应参数的脉冲频率的脉冲形式的多个信号。 从这些信号提供给状态寄存器的每个脉冲导致产生中央处理单元的中断请求信号。 中央处理单元控制掩模寄存器，该掩码寄存器又控制选通地屏蔽或禁止将脉冲从一个或多个传感器应用到状态寄存器的选通布置，使得在接收到第一个中断请求信号时，中央处理单元可以屏蔽所有 传感器，而是负责中断请求信号的传感器，并且通过测量随后产生的中断请求信号之间的间隔继续计算与之相关的参数，这种测量是通过执行增量指令来执行的。 内部定时和标志的使用提供不同参数的连续值的计算及其周期性显示。

    Apparatus for engine control
    50.
    发明授权
    Apparatus for engine control 失效
    发动机控制装置

    公开(公告)号：US4181944A

    公开(公告)日：1980-01-01

    申请号：US924819

    申请日：1978-07-14

    申请人： Teruo Yamauchi ,  Yoshishige Oyama ,  Nobuaki Miyakawa

    发明人： Teruo Yamauchi ,  Yoshishige Oyama ,  Nobuaki Miyakawa

    IPC分类号： F02B1/04 ,  F02B75/02 ,  F02D41/26 ,  F02D45/00 ,  F02M25/07 ,  F02P5/15 ,  F02P5/152 ,  F02P5/153 ,  G06F15/20 ,  F02D5/00

    CPC分类号： F02P5/151 ,  F02D41/26 ,  F02P5/15 ,  F02B1/04 ,  F02B2075/027 ,  Y02T10/46

    摘要： An apparatus for the optimum control of a combustion engine, which is capable of compensating for the change in the combustion engine with time caused by mechanical wear. An optimum control value is stored in a memory. The data stored in the memory is compared in a microcomputer with an output from at least one sensor for detecting the operating conditions of the combustion engine, so that the optimum control signal for the present operating conditions is applied to the control apparatus for the combustion engine. In response to an output from a combustion pressure sensor for detecting the change with time of the combustion engine, calculations for correcting the data in the memory are conducted, followed by the updating of the data therein.

    摘要翻译： 一种用于内燃机的最佳控制的装置，其能够随着机械磨损引起的时间补偿内燃机的变化。 最佳控制值存储在存储器中。 存储在存储器中的数据在微计算机中与来自至少一个传感器的输出进行比较，用于检测内燃机的操作条件，使得用于当前操作条件的最佳控制信号被施加到用于内燃机的控制装置 。 响应于用于检测内燃机的随时间变化的燃烧压力传感器的输出，进行用于校正存储器中的数据的计算，随后更新其中的数据。