公开(公告)号：US4842041A

公开(公告)日：1989-06-27

申请号：US137755

申请日：1987-12-24

申请人： Yuichi Sato ,  Takashi Sato ,  Toshio Yamada

发明人： Yuichi Sato ,  Takashi Sato ,  Toshio Yamada

IPC分类号： B22D11/06

CPC分类号： B22D11/0642

摘要： In the continuous manufacturing of metal strip from molten alloy, the nozzle from which the melt issues to form the continuous strip by rapid-cooling solidification has an orifice that is discontinuous in the width direction of the strip; i.e., it is a multiple orifice. This enables amorphous and crystalline continuous metal strip to be produced in much greater widths than has hitherto been possible, and the strip thus produced is more uniform in thickness.

公开(公告)号：US08300118B2

公开(公告)日：2012-10-30

申请号：US13427273

申请日：2012-03-22

申请人： Masato Yoneda ,  Toshio Yamada

发明人： Masato Yoneda ,  Toshio Yamada

IPC分类号： H04N5/262 ,  H04N5/228 ,  H04N5/235 ,  H04N5/76 ,  H04N5/335 ,  H04N5/238 ,  G03B7/00

CPC分类号： H04N5/2628 ,  H04N5/232 ,  H04N5/23296 ,  H04N5/3532 ,  H04N5/374

摘要： An imaging method includes a step of setting, when a digital zoom operation mode for enlarging an image imaged by a imaging part of an X-Y address type is selected, a zoom magnification and enlarging the image at the zoom magnification set. The imaging method includes the steps of: setting an imaging range in a vertical direction of the imaging part according to the zoom magnification set in the digital zoom step; outputting a driving signal for scanning the shutter signal and the readout signal to perform exposure in the imaging range set in the imaging range setting step and driving the imaging part; and discarding, when the zoom magnification is changed in the digital zoom step, images imaged by the imaging part before and after the change of the zoom magnification to prevent the images from being used.

公开(公告)号：US08133841B2

公开(公告)日：2012-03-13

申请号：US12025377

申请日：2008-02-04

申请人： Naomi Noda ,  Yukio Miyairi ,  Toshio Yamada

发明人： Naomi Noda ,  Yukio Miyairi ,  Toshio Yamada

IPC分类号： B01J23/02

CPC分类号： B01J35/04 ,  B01D46/2429 ,  B01D46/2466 ,  B01D2046/2437 ,  B01D2046/2496 ,  B01D2279/30 ,  B01J23/63 ,  B01J35/023 ,  B01J35/10 ,  B01J37/0036 ,  B01J37/0234 ,  F01N3/0222 ,  F01N2510/06 ,  F01N2510/0682 ,  Y02T10/20

摘要： According to the present invention, there is provided a honeycomb catalytic structure comprising: a honeycomb structure comprising porous partition walls having a large number of pores, disposed so as to form a plurality of cells extending between the two end faces of the honeycomb structure and plugging portions disposed at either one end of each cell, and a catalyst layer containing a catalyst, supported at least on the inner surfaces of the pores of the honeycomb structure, wherein the mass of the catalyst layer per unit volume (1 cm3) of the honeycomb structure (g/cm3) is 60% or less of the volume of pores per unit volume (1 cm3) of the honeycomb structure (cm3/cm3).

摘要翻译： 根据本发明，提供了一种蜂窝状催化剂结构体，其特征在于，包括：蜂窝结构体，其具有多孔分隔壁，所述蜂窝结构体具有多个孔，所述蜂窝结构体设置成形成在所述蜂窝结构体的两个端面之间延伸的多个孔， 设置在每个单元的任一端的部分和至少支撑在蜂窝结构的孔的内表面上的含有催化剂的催化剂层，其中每单位体积（1cm 3）的蜂窝体的催化剂层的质量 结构（g / cm 3）为每单位体积（1cm 3）的蜂窝结构体积（cm 3 / cm 3）的孔的体积的60％以下。

公开(公告)号：US20110062990A1

公开(公告)日：2011-03-17

申请号：US12871529

申请日：2010-08-30

申请人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

发明人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K3/356165 ,  H03K3/012 ,  H03K3/356182 ,  H03K19/018507

摘要： A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

摘要翻译： 如果在上拉电路（总线保持电路）的电源电压和输入端子之间发生电位差，则上拉电路防止产生泄漏电流。 总线保持电路中设置有控制端子。 输入端子和控制端子的输入被输入到或非门，并且NOR门的输出被输入到控制输入端子和总线保持电源电压之间的耦合的第一MOSFET的栅极端子 电路。 提供第二个MOSFET（“控制”MOSFET）作为通过控制端子的反相输出操作的开关。 通过串联耦合第一个MOSFET和控制MOSFET，可以以更高的精度控制输入端子和电源电压之间的耦合，从而防止漏电流的产生。

公开(公告)号：US20100180859A1

公开(公告)日：2010-07-22

申请号：US12601200

申请日：2008-05-20

申请人： Koichi Hatamura ,  Toshio Yamada ,  Atsushi Morita

发明人： Koichi Hatamura ,  Toshio Yamada ,  Atsushi Morita

IPC分类号： F02B17/00 ,  F02B47/08

CPC分类号： F02D13/0207 ,  F01L1/08 ,  F01L1/185 ,  F01L1/267 ,  F01L3/06 ,  F01L13/0026 ,  F01L13/0063 ,  F01L2001/0537 ,  F01L2013/0068 ,  F01L2105/00 ,  F01L2800/10 ,  F01L2820/01 ,  F02B1/12 ,  F02B17/00 ,  F02B23/104 ,  F02B27/04 ,  F02B2075/125 ,  F02D13/0246 ,  F02D13/0273 ,  F02D21/08 ,  F02M26/01 ,  Y02T10/123 ,  Y02T10/146 ,  Y02T10/18

摘要： A four-cycle engine including a blowdown pressure wave supercharging system (40) compressing and supplying exhaust gas into a second cylinder (#1) by causing a pressure wave (blowdown pressure wave) from a combustion chamber at opening of an exhaust valve of a first cylinder (#4) to act on an exhaust port (1e) of the second cylinder (#1) and during a reopen period of an exhaust valve of the second cylinder; and a mask member (50) restraining the exhaust gas (EGR gas) compressed and supplied into the second cylinder (#1) from mixing with fresh air flowing from an intake port (1d), wherein a first temperature layer (T1) at a high temperature containing a large amount of the EGR gas in the fresh air and a second temperature layer (T2) at a temperature lower than that of the first temperature layer (T1) containing a smaller amount of the EGR gas than that of the first temperature layer (T1) in the fresh air are formed in the second cylinder (#1).

摘要翻译： 一种四冲程发动机，其包括排污压力波增压系统（40），其通过在燃烧室的打开时产生来自燃烧室的压力波（排污压力波），将排气压缩并供给到第二气缸（＃1） 第一气缸（＃4）作用在第二气缸（＃1）的排气口（1e）上，并且在第二气缸的排气阀的重新开启期间; 以及抑制压缩并供给到所述第二气缸（＃1）中的排气（EGR气体）与从进气口（1d）流出的新鲜空气混合的掩模构件（50），其中，所述第一温度层（T1） 在新鲜空气中含有大量EGR气体的高温和比第一温度层（T1）低的温度的第二温度层（T2），其含有比第一温度更低的EGR气体量 在第二气缸（＃1）中形成新鲜空气中的层（T1）。

公开(公告)号：US07488368B2

公开(公告)日：2009-02-10

申请号：US11252758

申请日：2005-10-19

申请人： Toshio Yamada ,  Tatsuhiko Hatano

发明人： Toshio Yamada ,  Tatsuhiko Hatano

IPC分类号： B01D46/00 ,  B01D39/20 ,  F01N3/022

CPC分类号： B28B11/006 ,  F01N3/0222 ,  F01N2330/06 ,  F01N2330/30 ,  Y02T10/20 ,  Y10S55/05 ,  Y10S55/10 ,  Y10S55/30 ,  Y10S264/48 ,  Y10T428/24149

摘要： The ceramic honeycomb structure has a plurality of cells partitioned by porous partition walls and extending through the structure in an axial direction, one end portion of a predetermined cell is plugged with a plugging portion constituted of a plugging material with which the cell is filled, and the other end portion of a remaining cell is plugged with the plugging portion on a side opposite to the end portion of the predetermined cell. In the ceramic honeycomb structure, a sectional numerical aperture of the plugging portion in the vicinity of the partition wall is smaller than that of the plugging portion in the vicinity of a central axis, and a difference between the sectional numerical apertures is 10% or more.

摘要翻译： 陶瓷蜂窝结构体具有由多孔分隔壁隔开并沿轴向延伸穿过结构体的多个单元，预定单元的一个端部用由填充单元的封孔材料构成的封堵部分堵塞，以及 剩余电池的另一端部与堵塞部分在与预定电池单元的端部相反的一侧插入。 在陶瓷蜂窝结构体中，分隔壁附近的封堵部的截面数值孔径小于中心轴附近的封堵部的数值孔径，并且区间数值孔径之间的差为10％以上 。

公开(公告)号：US20080013368A1

公开(公告)日：2008-01-17

申请号：US11826636

申请日：2007-07-17

申请人： Ryo Mori ,  Toshio Yamada ,  Tetsuya Muraya

发明人： Ryo Mori ,  Toshio Yamada ,  Tetsuya Muraya

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.

摘要翻译： 本发明提供一种半导体集成电路器件，其具有泄漏电流降低的SRAM。 在包括多个存储单元的SRAM中，每个存储单元由两个反相器电路的输入和输出端子交叉存储的存储器构成，以及设置在存储和互补位线之间并且其栅极连接到字线的选择MOSFET， 提供了衬底偏置开关电路。 在正常操作中，衬底偏置开关电路将电源电压提供给形成存储单元的P沟道MOSFET的N型阱，并将电路的接地电位提供给P型阱，其中， 形成N沟道MOSFET。 在待机状态下，衬底偏置开关电路提供低于电源电压的预定电压，并且N型阱和P沟道MOSFET的源极之间的PN结未被正向偏置到N 并且提供比地电位高的预定电压，并且P型阱和N沟道MOSFET的源极之间的PN结未被正向偏置到P型阱。

公开(公告)号：US20070198880A1

公开(公告)日：2007-08-23

申请号：US11785213

申请日：2007-04-16

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/1806 ,  G11C2029/2602 ,  G11C2029/3202

摘要： There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

公开(公告)号：US20060187734A1

公开(公告)日：2006-08-24

申请号：US11377348

申请日：2006-03-17

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

公开(公告)号：US07046573B2

公开(公告)日：2006-05-16

申请号：US10748137

申请日：2003-12-31

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C7/00

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.