公开(公告)号：US12131991B2

公开(公告)日：2024-10-29

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5283 ,  H01L29/41725 ,  H01L29/4232

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US12036578B1

公开(公告)日：2024-07-16

申请号：US16424338

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  James M. Blackwell ,  Eungnak Han ,  Rami Hourani ,  Tayseer Mahdi

IPC: B05D3/00 ,  B01J19/00 ,  B05D3/10 ,  C07F9/28 ,  C07F9/38 ,  C07F9/40 ,  C25D11/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H05K1/18

CPC classification number: B05D3/002 ,  B01J19/006 ,  B05D3/10 ,  C07F9/28 ,  C07F9/38 ,  C07F9/40 ,  C07F9/4021 ,  C25D11/00 ,  H01L21/56 ,  H01L21/76831 ,  H01L23/293 ,  H01L23/5226 ,  H05K1/181 ,  H05K2201/0137 ,  H05K2201/0195

Abstract: Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization having an initiator as the SAM or the SAM attached to another SAM. Other embodiments may be described and/or claimed.

公开(公告)号：US12012473B2

公开(公告)日：2024-06-18

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: G03F7/11 ,  C08F265/02 ,  C08F265/04 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US20240194483A1

公开(公告)日：2024-06-13

申请号：US18064352

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Florian Gstrein ,  Gurpreet Singh

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/088

Abstract: A cross-linkable diblock copolymer can facilitate multi-pitch patterning for forming an IC device. The IC device may include a metal layer with different pitches. The metal layer may include a first region having a first pitch and a second region having a second pitch that is greater than the first pitch. The cross-linkable diblock copolymer may be deposited over the metal layer. The portion of the diblock copolymer over the second region may be exposed to light (e.g., UV), which causes cross-linking of functional groups in the diblock copolymer. The cross-linking may form a structure that includes an amorphous phase of the diblock copolymer. The structure may be over and aligned with the second region of the metal layer. After the structure is formed, the diblock copolymer over the first region may self-assemble and form lamellar structures that are aligned with metal lines and insulative structures in the first region.

公开(公告)号：US11417567B2

公开(公告)日：2022-08-16

申请号：US16347184

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Eungnak Han ,  Rami Hourani ,  Ruth A. Brain ,  Paul A. Nyhus ,  Manish Chandhok ,  Charles H. Wallace ,  Chi-Hwa Tsang

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

公开(公告)号：US20220199540A1

公开(公告)日：2022-06-23

申请号：US17125232

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Marie Krysak ,  Brandon Jay Holybee ,  Florian Gstrein

IPC: H01L23/538

Abstract: Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via.

公开(公告)号：US20220199420A1

公开(公告)日：2022-06-23

申请号：US17124730

申请日：2020-12-17

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Eungnak Han ,  Manish Chandhok ,  Richard E. Schenker ,  Florian Gstrein ,  Paul A. Nyhus ,  Charles Henry Wallace

IPC: H01L21/311 ,  H01L21/768

Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：US11262654B2

公开(公告)日：2022-03-01

申请号：US16728976

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Lauren Doyle ,  Marie Krysak ,  Patrick Theofanis ,  James Blackwell ,  Eungnak Han

IPC: G03F7/039 ,  C08G83/00 ,  C08F20/24 ,  C08F30/08 ,  G03F7/20

Abstract: Chain scission resist compositions suitable for EUV lithography applications may include monomer functional groups that improve the kinetics and/or thermodynamics of the scission mechanism. Chain scission resists may include monomer functional groups that reduce the risk that leaving groups generated through the scission mechanism may chemically corrode processing equipment.

公开(公告)号：US20210375745A1

公开(公告)日：2021-12-02

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: H01L23/528 ,  H01L23/522

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US20210371566A1

公开(公告)日：2021-12-02

申请号：US17313932

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.