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    INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED NEIGHBORING PARTITIONED SOURCE OR DRAIN CONTACT STRUCTURES
    41.
    发明申请
    INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED NEIGHBORING PARTITIONED SOURCE OR DRAIN CONTACT STRUCTURES 审中-公开

    公开(公告)号：US20200075770A1

    公开(公告)日：2020-03-05

    申请号：US16122277

    申请日：2018-09-05

    Applicant: Intel Corporation

    Inventor： Mauro J. KOBRINSKY ,  Stephanie BOJARSKI ,  Myra MCDONNELL ,  Tahir GHANI

    IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238

    Abstract: Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures are described. An integrated circuit structure includes a first gate stack over a first fin, and a second gate stack over a second fin. First and second epitaxial source or drain structures are at first and second ends of the first fin. Third and fourth epitaxial source or drain structures are at first and second ends of the second fin. A first conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures, and has a first portion partitioned from a second portion. A second conductive contact structure is coupled to one of the third or the fourth epitaxial source or drain structures, and has a first portion partitioned from a second portion. The second conductive contact structure is neighboring the first conductive contact structure and has a composition different than a composition of the first conductive contact structure.

    DOUBLE GATED THIN FILM TRANSISTORS
    43.
    发明申请
    DOUBLE GATED THIN FILM TRANSISTORS 审中-公开

    公开(公告)号：US20200006573A1

    公开(公告)日：2020-01-02

    申请号：US16022480

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Gilbert DEWEY ,  Willy RACHMADY

    IPC: H01L29/786 ,  H01L29/423

    Abstract: Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.

    SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN
    49.
    发明申请
    SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN 审中-公开

    公开(公告)号：US20190172941A1

    公开(公告)日：2019-06-06

    申请号：US16304620

    申请日：2016-07-02

    Applicant: INTEL CORPORATION

    Inventor： Willy RACHMADY ,  Sanaz K. GARDNER ,  Chandra S. MOHAPATRA ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775

    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

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