公开(公告)号：US20170092763A1

公开(公告)日：2017-03-30

申请号：US15377722

申请日：2016-12-13

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Effendi Leobandung ,  Amlan Majumdar ,  Renee T. Mo ,  Yanning Sun

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/32 ,  H01L29/66 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L21/2258 ,  H01L21/31105 ,  H01L21/31116 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

公开(公告)号：US09502562B2

公开(公告)日：2016-11-22

申请号：US14945912

申请日：2015-11-19

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7841 ,  H01L29/785

Abstract: Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

公开(公告)号：US09484463B2

公开(公告)日：2016-11-01

申请号：US14197655

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/78 ,  H01L29/205 ,  H01L29/66 ,  H01L29/201 ,  H01L29/778

CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

Abstract translation: 一种用于制造多重装置的方法包括在多重装置的衬底上形成翅片，翅片由半导体材料形成，在鳍片和衬底上直接生长第一共形外延层，其中第一共形外延层是高度掺杂的 直接在所述第一共形外延层上生长第二共形外延层，其中所述第二共形外延层是高度掺杂的，选择性地去除所述第二外延层的一部分以暴露所述第一共形外延层的一部分， 第一共形外延层以暴露鳍的一部分，从而形成沟槽，并在沟槽内形成栅极。

公开(公告)号：US09472658B2

公开(公告)日：2016-10-18

申请号：US14962268

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L21/285 ,  H01L21/768 ,  H01L29/06 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/10 ,  H01L29/207

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/02636 ,  H01L21/28575 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/207 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522

Abstract: A method for fabricating a III-V nanowire. The method may include providing a semiconductor substrate, which includes an insulator, with a wide-bandgap layer on the top surface of the semiconductor substrate; etching the insulator to suspend the wide-bandgap layer; growing a compositionally-graded channel shell over the wide-bandgap layer; forming a gate structure forming spacers on the sidewalls of the gate structure; and forming a doped raised source drain region adjacent to the spacers.

公开(公告)号：US20160149054A1

公开(公告)日：2016-05-26

申请号：US14938904

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Cheng-Wei Cheng ,  Wilfried E. Haensch ,  Amlan Majumdar ,  Kuen-Ting Shiu

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/152 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78642

Abstract: An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.

Abstract translation: 形成具有受控栅极重叠的垂直场效应晶体管的半导体结构的方法。 该方法包括在半导体衬底上形成第一半导体层，第二半导体层，第三半导体层，第四半导体层，第五半导体层和第一电介质层。 蚀刻的第一介电层和第一漏极接触被第一间隔物包围。 第一漏极接触由第五半导体层构成。 形成由第四半导体层，由第三半导体层构成的沟道和由第二半导体层构成的第二源极触点构成的第二漏极接触。 此外，形成由第一半导体构成的第一源极接触，并且在围绕第一柱和第二柱的一部分的第一源极接触层的一部分上形成栅电极。

公开(公告)号：US09337309B1

公开(公告)日：2016-05-10

申请号：US14802722

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/88 ,  H01L21/329 ,  H01L29/74 ,  H01L29/788 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66666 ,  H01L29/0603 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/7827 ,  H01L29/78609 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

公开(公告)号：US09299615B1

公开(公告)日：2016-03-29

申请号：US14578934

申请日：2014-12-22

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L21/8238 ,  H01L21/338 ,  H01L21/84 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/12 ,  H01L29/20

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/78696

Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.

公开(公告)号：US20150325650A1

公开(公告)日：2015-11-12

申请号：US14793772

申请日：2015-07-08

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Amlan Majumdar ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/28575 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/778 ,  H01L29/7784

Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.

公开(公告)号：US20150255568A1

公开(公告)日：2015-09-10

申请号：US14197746

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： ANIRBAN BASU ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.

Abstract translation: 一种用于制造多重装置的方法包括在多重装置的衬底上形成翅片，翅片由半导体材料形成，直接在翅片和衬底上生长第一共形外延层，其中第一共形外延层未掺杂或 轻掺杂，直接在第一共形外延层上生长第二共形外延层，其中第二共形外延层是高度掺杂的，选择性地去除第二外延层的一部分以暴露第一共形外延层的一部分，从而形成 沟槽，并在沟槽内形成栅极。

公开(公告)号：US20150255567A1

公开(公告)日：2015-09-10

申请号：US14197655

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

Abstract translation: 一种用于制造多重装置的方法包括在多重装置的衬底上形成翅片，翅片由半导体材料形成，在鳍片和衬底上直接生长第一共形外延层，其中第一共形外延层是高度掺杂的 直接在所述第一共形外延层上生长第二共形外延层，其中所述第二共形外延层是高度掺杂的，选择性地去除所述第二外延层的一部分以暴露所述第一共形外延层的一部分， 第一共形外延层以暴露鳍的一部分，从而形成沟槽，并在沟槽内形成栅极。