公开(公告)号：US20180181774A1

公开(公告)日：2018-06-28

申请号：US15389078

申请日：2016-12-22

Applicant: International Business Machines Corporation

Inventor： Richard H. Boivie ,  Eduard A. Cartier ,  Daniel J. Friedman ,  Kohji Hosokawa ,  Charanjit Jutla ,  Wanki Kim ,  Chandrasekara Kothandaraman ,  Chung Lam ,  Frank R. Libsch ,  Seiji Munetoh ,  Ramachandran Muralidhar ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Robert L. Wisnieff

IPC: G06F21/72 ,  G06F21/75 ,  H01L27/112 ,  H01L23/00

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

公开(公告)号：US20170309723A1

公开(公告)日：2017-10-26

申请号：US15474482

申请日：2017-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  John Bruley ,  Eduard A. Cartier ,  Martin M. Frank ,  Vijay Narayanan ,  John Rozen

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/28255 ,  H01L21/28229 ,  H01L21/28264 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

公开(公告)号：US20160380076A1

公开(公告)日：2016-12-29

申请号：US15258597

申请日：2016-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09472643B2

公开(公告)日：2016-10-18

申请号：US14595756

申请日：2015-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09443953B1

公开(公告)日：2016-09-13

申请号：US14833215

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kevin K. Chan ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/31051 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/78

Abstract: A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate, where the source and the drain are positioned under the spacers. An interlayer dielectric is formed on top of the substrate, the spacers, and the dummy gate. The interlayer dielectric is planarized along with part of the spacers and the dummy gate. The dummy gate is removed, thereby leaving an opening. A sacrificial layer is deposited on top of the substrate in a bottom of the opening. The sacrificial layer includes at least one of silicon germanium and/or germanium. The sacrificial layer is removed from the substrate in the bottom of the opening, thereby growing an interfacial oxide layer on the substrate in the opening. A high-κ dielectric layer is deposited on top of the interfacial oxide layer.

Abstract translation: 技术涉及形成晶体管。 在两面具有间隔物的基板上形成虚拟栅极。 源极和漏极形成在衬底中，其中源极和漏极位于间隔物下方。 在基板，间隔件和虚拟栅极的顶部上形成层间电介质。 层间介质与间隔物和虚拟栅极的一部分一起被平坦化。 去除虚拟门，从而留下一个开口。 牺牲层沉积在开口底部的衬底的顶部上。 牺牲层包括硅锗和/或锗中的至少一种。 牺牲层从开口底部的基底上去除，从而在开口中的基底上生长界面氧化物层。 高介电层沉积在界面氧化物层的顶部。

公开(公告)号：US20160181353A1

公开(公告)日：2016-06-23

申请号：US14572974

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Abstract translation: 一种包括在绝缘层和衬底之间的深沟槽电容器的绝缘层的一侧上形成氧吸气层的方法，所述吸氧层包括含铝化合物，并且在绝缘层的顶部上沉积内电极， 内部电极包括金属。

公开(公告)号：US09349832B1

公开(公告)日：2016-05-24

申请号：US14950388

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kevin K. Chan ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/31051 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/78

Abstract: A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate, where the source and the drain are positioned under the spacers. An interlayer dielectric is formed on top of the substrate, the spacers, and the dummy gate. The interlayer dielectric is planarized along with part of the spacers and the dummy gate. The dummy gate is removed, thereby leaving an opening. A sacrificial layer is deposited on top of the substrate in a bottom of the opening. The sacrificial layer includes at least one of silicon germanium and/or germanium. The sacrificial layer is removed from the substrate in the bottom of the opening, thereby growing an interfacial oxide layer on the substrate in the opening. A high-κ dielectric layer is deposited on top of the interfacial oxide layer.

Abstract translation: 技术涉及形成晶体管。 在两面具有间隔物的基板上形成虚拟栅极。 源极和漏极形成在衬底中，其中源极和漏极位于间隔物下方。 在基板，间隔件和虚拟栅极的顶部上形成层间电介质。 层间介质与间隔物和虚拟栅极的一部分一起被平坦化。 去除虚拟门，从而留下一个开口。 牺牲层沉积在开口底部的衬底的顶部上。 牺牲层包括硅锗和/或锗中的至少一种。 牺牲层从开口底部的基底上去除，从而在开口中的基底上生长界面氧化物层。 高科技 介电层沉积在界面氧化物层的顶部。

公开(公告)号：US20150236135A1

公开(公告)日：2015-08-20

申请号：US14699427

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US20140195175A1

公开(公告)日：2014-07-10

申请号：US13734075

申请日：2013-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eduard A. Cartier ,  Charles LaRow ,  Travis S. Merrill ,  Ernest Y. Wu

IPC: G01R31/14 ,  G06F17/10

CPC classification number: G06F17/10 ,  G01R31/129 ,  G01R31/3008

Abstract: Embodiments of the present invention provide a method, system, and program product for testing a semiconductor device to measure dielectric breakdown. A computer applies a plurality of stress voltages to a semiconductor device under test. The computer determines a plurality of current measurements until a failure criteria occurs, using a predefined voltage ramp rate and a predefined plurality of stress voltage steps, wherein the number of the plurality of current measurements is less than or equal to the number of the predefined plurality of voltage steps. The computer identifies a stress voltage at which the semiconductor device fails. The computer calculates a frequency dependent voltage acceleration factor based on the quotient of the natural log of the voltage at which the semiconductor device under test failed to the natural log of the predetermined voltage ramp rate.

Abstract translation: 本发明的实施例提供了一种用于测试半导体器件以测量电介质击穿的方法，系统和程序产品。 计算机对被测半导体器件施加多个应力电压。 计算机使用预定义的电压斜坡率和预定义的多个应力电压步骤来确定多个电流测量直到发生故障标准，其中多个电流测量的数量小于或等于预定义多个的数量 的电压步进。 计算机识别半导体器件失效的应力电压。 计算机根据被测半导体器件的电压的自然对数的商与预定电压斜坡率的自然对数计算频率相关的电压加速因子。

公开(公告)号：US08766378B2

公开(公告)日：2014-07-01

申请号：US13803470

申请日：2013-03-14

Applicant: International Business Machines Corporation

Inventor： Eduard A. Cartier ,  Qingqing Liang ,  Yue Liang ,  Yanfeng Wang

IPC: H01L29/78

CPC classification number: H01L29/408 ,  G06F17/5045 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.

Abstract translation: 使用高k电介质金属栅Vt移位效应提供可编程场效应晶体管（FET）及其制造方法。 控制高k电介质金属栅极结构中的Vt漂移的方法包括向高k电介质金属栅极结构的栅极接触施加电流以升高形成栅极叠层的金属的温度。 温度升高超过Vt转换温度阈值以提供导通状态。