公开(公告)号：US10564125B2

公开(公告)日：2020-02-18

申请号：US15841907

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Heng Wu

IPC: G01N27/68 ,  B82B3/00 ,  B82B1/00

Abstract: A method of forming a semiconductor structure includes forming a substrate, forming an anchor layer, and forming one or more self-aligned nanotip pillar pairs disposed vertically between the substrate and the anchor layer. A given one of the nanotip pillar pairs comprises a bottom nanotip pillar and a top nanotip pillar, the bottom nanotip pillar comprising a base portion disposed on a top surface of the substrate and the top nanotip pillar comprising a base portion disposed in the anchor layer. The bottom nanotip pillar and the top nanotip pillar comprise sidewalls that taper to points as distance from the respective base portions increases.

公开(公告)号：US10559491B2

公开(公告)日：2020-02-11

申请号：US16013010

申请日：2018-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Sebastian Naczas ,  Heng Wu ,  Peng Xu

IPC: H01L21/76 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.

公开(公告)号：US20190393345A1

公开(公告)日：2019-12-26

申请号：US16291931

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Peng Xu ,  Heng Wu ,  Zhenxing Bi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

Abstract: An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.

公开(公告)号：US10510885B1

公开(公告)日：2019-12-17

申请号：US16291367

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Peng Xu ,  Heng Wu ,  Zhenxing Bi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/02

Abstract: An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.

公开(公告)号：US20190333997A1

公开(公告)日：2019-10-31

申请号：US16509061

申请日：2019-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/10 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308

Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.

公开(公告)号：US10332983B1

公开(公告)日：2019-06-25

申请号：US15935468

申请日：2018-03-26

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/225 ,  H01L21/02 ,  H01L29/423

Abstract: Vertical field-effect transistors are fabricated while controlling gate length by causing enhanced oxidation of silicon germanium regions on parallel semiconductor fin channel regions. Oxidation of the silicon germanium region is accompanied by volume expansion and condensation. Shared or non-shared gate structures are formed on the sidewalls of the semiconductor fin channel regions. A dielectric liner may be incorporated with self-aligned oxide regions to form a composite spacer for providing electrical isolation of the top source/drain regions.

公开(公告)号：US10319835B2

公开(公告)日：2019-06-11

申请号：US15813528

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Zuoguang Liu ,  Heng Wu ,  Tenko Yamashita

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

公开(公告)号：US20190164843A1

公开(公告)日：2019-05-30

申请号：US15824537

申请日：2017-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31133 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.

公开(公告)号：US20180308743A1

公开(公告)日：2018-10-25

申请号：US16013010

申请日：2018-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Sebastian Naczas ,  Heng Wu ,  Peng Xu

IPC: H01L21/764 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.

公开(公告)号：US20180212039A1

公开(公告)日：2018-07-26

申请号：US15835925

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robinhsinku Chao ,  ChoongHyun Lee ,  Heng Wu ,  Chun W. Yeung ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/324

CPC classification number: H01L29/78618 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: Methods of forming a semiconductor device include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.