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41.
公开(公告)号:US10132836B2
公开(公告)日:2018-11-20
申请号:US14708198
申请日:2015-05-09
Applicant: International Business Machines Corporation
Inventor: Bing Dang , John Knickerbocker , Yang Liu , Maurice Mason , Lubomyr T. Romankiw
Abstract: A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.
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公开(公告)号:US12300615B2
公开(公告)日:2025-05-13
申请号:US18056393
申请日:2022-11-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Mukta Ghate Farooq , Qianwen Chen , Shahid Butt , Eric Perfecto , Michael P. Belyansky , Katsuyuki Sakuma , John Knickerbocker
IPC: H01L23/535 , B32B43/00 , H01L21/683 , H01L23/522 , H01L23/528
Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.
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公开(公告)号:US12170252B2
公开(公告)日:2024-12-17
申请号:US17449280
申请日:2021-09-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Lei Shan , Daniel Joseph Friedman , Griselda Bonilla , John Knickerbocker
IPC: H01L23/538 , H01L21/48 , H01L23/15 , H01L23/498
Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.
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公开(公告)号:US20240282658A1
公开(公告)日:2024-08-22
申请号:US18169998
申请日:2023-02-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: John Knickerbocker , Mukta Ghate Farooq , Keiji Matsumoto
IPC: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/29 , H01L23/367
CPC classification number: H01L23/3185 , H01L21/561 , H01L23/29 , H01L23/291 , H01L23/3192 , H01L23/3675 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/95 , H01L2224/16225 , H01L2224/2732 , H01L2224/2741 , H01L2224/2745 , H01L2224/27462 , H01L2224/2783 , H01L2224/29083 , H01L2224/29111 , H01L2224/29139 , H01L2224/29147 , H01L2224/29181 , H01L2224/29186 , H01L2224/2919 , H01L2224/32153 , H01L2224/32221 , H01L2224/33183 , H01L2224/95 , H01L2924/0132 , H01L2924/0133 , H01L2924/04953 , H01L2924/07025
Abstract: A semiconductor integrated circuit device includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting solder at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
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公开(公告)号:US20240194555A1
公开(公告)日:2024-06-13
申请号:US18080034
申请日:2022-12-13
Applicant: International Business Machines Corporation
Inventor: Mukta Ghate Farooq , Keiji Matsumoto , John Knickerbocker
CPC classification number: H01L23/3192 , H01L23/29 , H01L23/291 , H01L23/3185 , H01L23/481 , H01L24/16
Abstract: A semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
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公开(公告)号:US20220200086A1
公开(公告)日:2022-06-23
申请号:US17128371
申请日:2020-12-21
Applicant: International Business Machines Corporation
Inventor: Qianwen Chen , Jae-Woong Nah , Bing Dang , Leanna Pancoast , John Knickerbocker
IPC: H01M50/171 , H01M10/0585 , H01M50/186 , H01M50/197 , H01M50/191
Abstract: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.
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公开(公告)号:US20210280834A1
公开(公告)日:2021-09-09
申请号:US16813071
申请日:2020-03-09
Applicant: International Business Machines Corporation
Inventor: Bing Dang , Leanna Pancoast , Jae-Woong Nah , John Knickerbocker
IPC: H01M2/02 , H01M10/052 , H01M2/30 , H01M10/04
Abstract: Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.
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公开(公告)号:US20210265606A1
公开(公告)日:2021-08-26
申请号:US16796636
申请日:2020-02-20
Applicant: International Business Machines Corporation
Inventor: Bing Dang , John Knickerbocker , Qianwen Chen
IPC: H01M2/02 , H01M2/20 , H01M10/0585
Abstract: Thin Film Batteries are made of battery layers. Each battery layer has a substrate with one or more battery structures on the substrate surface. The battery structures have a first electrode connection and a second electrode, a first electrode (e.g. a cathode or anode) is electrically connected to the first electrode connection and a second electrode (e.g. an anode or cathode) is electrically connected to the second electrode connection. An electrolyte is at least partial disposed between and electrically connected to the first and second electrodes. A first edge connection on one of the substrate edges is physically and electrically connected to the first electrode connection. A second edge connection on one of the substrate edges is physically and electrically connected to the second electrode connection. An electrically insulating lamination is disposed on the substrate and covers the components except for the first and second edge connections, connected to respective battery electrodes. A first stack external connection electrical connects two or more of the first edge connections and a second stack external connection electrical connects two or more of the second edge connections. A first and second battery pole are connected to the respective first and second stack external connections. The TFBs are hermetically sealed.
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公开(公告)号:US20210249381A1
公开(公告)日:2021-08-12
申请号:US16788459
申请日:2020-02-12
Applicant: International Business Machines Corporation
Inventor: John Knickerbocker
IPC: H01L25/065 , H01L23/538 , H01L23/00 , H01L25/00 , H01L21/56
Abstract: Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface. The bridge is disposed on the substrate between the first semiconductor chip and the second semiconductor chip, and one or more of the smaller first chip connections is physically and electrically connected to a respective first bridge connection on the first part of the bridge surface and one or more of the smaller second chip connection is physically and electrically connected to a respective second bridge connection. Some embodiments, a large surface bridge with the bridge. The large surface bridge and bridge can have different configurations. The bridge thickness allows larger chip connections and smaller connections with high pitch to intermingled in a location within the module. Methods of manufacture are disclosed.
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公开(公告)号:US10964925B2
公开(公告)日:2021-03-30
申请号:US16283654
申请日:2019-02-22
Inventor: Bing Dang , Qianwen Chen , Yu Luo , John Knickerbocker , Jae-Woong Nah , Kai Liu , Po-wen Cheng , Tung-hsiu Shih , Mengnian Niu , Kai-wei Nieh
IPC: H01M2/06 , H01M2/30 , H01M10/0585 , H01M10/052
Abstract: Vertical via connections to a battery are hermetically sealed to prevent environmental factors (e.g. moisture, oxygen, and nitrogen) from entering the internals of the battery through porous conductive material filling the vias resulting in reduced battery performance and battery failure.
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