公开(公告)号：US09564439B2

公开(公告)日：2017-02-07

申请号：US15069578

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/308 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract translation: 提供了包含通过外延半导体堆叠与下层体硅衬底隔离的半导体鳍片的非平面半导体结构。 提供隔离的外延半导体材料堆叠包括从底部到顶部的包含至少一种导电类型的不同于形成半导体鳍片的特定器件区域的导电类型的掺杂剂的半导体冲击穿通停止器，以及 不含n型或p型掺杂剂的半导体扩散阻挡层。

公开(公告)号：US20160359003A1

公开(公告)日：2016-12-08

申请号：US15242992

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/10 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

Abstract translation: 一种制造半导体器件的方法，包括提供绝缘体上的应变硅（SSOI）结构，所述SSOI结构包括设置在衬底上的电介质层，设置在所述电介质层上的硅锗层和设置在所述绝缘体上的应变半导体材料层 直接在硅锗层上，在SSOI结构上形成多个鳍片，在nFET区域中的至少一个鳍片的一部分上形成栅极结构，在pFET区域中的至少一个鳍片的一部分上形成栅极结构 去除pFET区域中的至少一个鳍片的部分上的栅极结构，去除通过去除而暴露的硅锗层，并在pFET区域中的至少一个鳍片的部分上形成新的栅极结构， 新的门结构围绕四面的部分。

公开(公告)号：US20160225677A1

公开(公告)日：2016-08-04

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/84 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域

公开(公告)号：US20160027789A1

公开(公告)日：2016-01-28

申请号：US14874389

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： John E. Barth, JR. ,  Kangguo Cheng ,  Bruce B. Doris ,  Herbert L. Ho ,  Ali Khakifirooz ,  Babar A. Khan ,  Shom Ponoth ,  Kern Rim ,  Kehan Tian ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L29/417 ,  H01L21/762 ,  H01L29/06 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L27/10879 ,  H01L21/283 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/945

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

公开(公告)号：US20150340291A1

公开(公告)日：2015-11-26

申请号：US14282050

申请日：2014-05-20

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.

Abstract translation: 形成半导体结构的方法包括形成具有未应变层，第一应变层和形成在非应变层和第一应变层之间的第二应变层的多层晶格匹配结构。 蚀刻多层结构中的第一开口并沉积具有与第二应变层相同的材料的第二应变填充材料。 蚀刻多层结构中的第二个开口，并且沉积具有与未应变层相同的材料的无约束填充材料。 然后将具有与第一应变层相同的材料的第一应变填充材料沉积在无约束填充物和第二应变填充物之间。 第二应变翅片由沉积的第二应变填充材料形成，第一应变翅片由沉积的第一应变填充材料形成，并且由沉积的无约束填充材料形成未应变翅片。

公开(公告)号：US09190329B1

公开(公告)日：2015-11-17

申请号：US14282050

申请日：2014-05-20

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.

Abstract translation: 形成半导体结构的方法包括形成具有未应变层，第一应变层和形成在非应变层和第一应变层之间的第二应变层的多层晶格匹配结构。 蚀刻多层结构中的第一开口并沉积具有与第二应变层相同的材料的第二应变填充材料。 蚀刻多层结构中的第二个开口，并且沉积具有与未应变层相同的材料的无约束填充材料。 然后将具有与第一应变层相同的材料的第一应变填充材料沉积在无约束填充物和第二应变填充物之间。 第二应变翅片由沉积的第二应变填充材料形成，第一应变翅片由沉积的第一应变填充材料形成，并且由沉积的无约束填充材料形成未应变翅片。

公开(公告)号：US20150206884A1

公开(公告)日：2015-07-23

申请号：US14158956

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

Abstract translation: 在形成用于存取晶体管的沟槽电容器以及源极和漏极区域和栅极结构之后，在每个源极区域的第一侧壁上形成介电隔离物，同时物理地暴露每个源极区域的第二侧壁和漏极区域的侧壁。 在去除沟槽顶部电介质部分期间，可以使用每个电介质间隔物作为蚀刻掩模，以形成用于形成带状结构的带状空腔。 可选地，可以进行半导体材料的选择性沉积以形成凸起的源极和漏极区域。 在这种情况下，升高的源极区域仅从第一侧壁生长并且不从第二侧壁生长。 凸起的源极区域可以在形成带状空腔期间用作蚀刻掩模的一部分。 带状结构形成为通过电介质间隔物与相邻的存取晶体管电隔离的自对准结构。

公开(公告)号：US09064739B2

公开(公告)日：2015-06-23

申请号：US14029585

申请日：2013-09-17

Applicant: International Business Machines Corporation

Inventor： Wilfried E. A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: H01L21/66 ,  G01B7/06 ,  H01L27/088

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

公开(公告)号：US08969155B2

公开(公告)日：2015-03-03

申请号：US13891212

申请日：2013-05-10

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/306 ,  H01L21/32 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/785

Abstract: Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different thicknesses.

Abstract translation: 公开了在同一集成电路上具有不同厚度的隔离区域的半导体散热片。 氮化物间隔件保护一些翅片的下部，而其他翅片在下部不具有间隔物。 翅片的暴露的下部被氧化以提供不同厚度的隔离区域。

公开(公告)号：US08962417B2

公开(公告)日：2015-02-24

申请号：US13833656

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Kern Rim ,  William K. Henson ,  Yue Liang ,  Xinlin Wang

IPC: H01L21/8238 ,  H01L21/425 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.

Abstract translation: 提供了包括位于硅锗（SiGe）沟道的表面上的p沟道场效应晶体管（pFET）器件的半导体结构，其中源极/漏极区的结型材突变。 通过在位于Si衬底之上的SiGe沟道层的正下方形成N或C掺杂的Si层来提供pFET器件的突发的源极/漏极结。 提供了一种结构，其中N或C掺杂的Si层（夹在SiGe沟道层和Si衬底之间）对于p型掺杂剂具有与覆盖的SiGe沟道层大致相同的扩散速率。 由于N或C掺杂的Si层和上覆的SiGe沟道层对于p型掺杂物具有基本上相同的扩散率，并且因为N或C掺杂的Si层阻碍p型掺杂剂扩散到下面的Si 衬底，可以形成突发的源极/漏极结。