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    Early overlay prediction and overlay-aware mask design
    41.
    发明授权
    Early overlay prediction and overlay-aware mask design 有权

    公开(公告)号：US09940429B2

    公开(公告)日：2018-04-10

    申请号：US14753344

    申请日：2015-06-29

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70633

    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

    Stitch-derived via structures and methods of generating the same
    42.
    发明授权
    Stitch-derived via structures and methods of generating the same 有权
    针迹衍生经结构及其生成方法

    公开(公告)号：US09454631B2

    公开(公告)日：2016-09-27

    申请号：US14285719

    申请日：2014-05-23

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522 ,  H01L21/768

    CPC classification number: G06F17/5068 ,  G06F17/50 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.

    Abstract translation: 通过级别的设计形状被映射到上层导线级别的线级设计形状设计的针脚区域。 对于不对应于通孔级设计形状的每个针脚区域，在底层导电线路层中提供通孔捕捉设计形状。 可以调整针迹区域和通孔捕捉设计形状的形状以符合设计规则约束。 此外，针迹可以可选地移动到相邻的线级设计形状中以解决设计规则冲突。 一旦所有通孔级设计形状被相应的针脚区域替换，修改后的设计布局可以消除通孔级设计形状，从而不需要提供通孔级光刻掩模。 体现修改后的设计布局的金属互连结构可以通过采用一组硬掩模层而不使用用于通孔级的光刻掩模来形成。

    MULTIPLE-DEPTH TRENCH INTERCONNECT TECHNOLOGY AT ADVANCED SEMICONDUCTOR NODES
    44.
    发明申请
    MULTIPLE-DEPTH TRENCH INTERCONNECT TECHNOLOGY AT ADVANCED SEMICONDUCTOR NODES 有权
    先进的半导体节点的多深度互联互连技术

    公开(公告)号：US20160042114A1

    公开(公告)日：2016-02-11

    申请号：US14883243

    申请日：2015-10-14

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  G03F7/20 ,  H01L21/308 ,  H01L21/67 ,  H01L21/768 ,  H01L21/027

    CPC classification number: G06F17/5081 ,  G03F7/2022 ,  G06F17/5077 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/76802 ,  H01L21/76816

    Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

    Abstract translation: 金属互连结构，系统和制造方法，其中设计布局包括形成不同沟槽深度的至少两个沟槽的结果。 该方法使用稍微改进的BEOL处理堆，以防止金属互连结构侵入下面的硬掩模电介质或金属硬掩模层。 因此，通过调整系统的参数并且允许由两个掩模曝光的区域具有更深的沟槽来获得两个沟槽深度。 这里，通过使用定义最低蚀刻深度的硬掩模来修改BEOL堆叠处理以实现两个沟槽深度。 该设计可以通过利用辅助沟槽深度来优化用于电迁移（或设置定时违反）的设计的软件来优化，检查电线周围的空间机会，推出电线以产生空间并将电线转换成深沟槽线。

    FLUXONIUM QUBIT AND DEVICES INCLUDING PLURALITY OF VERTICAL STACKS OF JOSEPHSON JUNCTIONS
    45.
    发明申请
    FLUXONIUM QUBIT AND DEVICES INCLUDING PLURALITY OF VERTICAL STACKS OF JOSEPHSON JUNCTIONS 审中-公开

    公开(公告)号：US20200335549A1

    公开(公告)日：2020-10-22

    申请号：US16387420

    申请日：2019-04-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Martin O. Sandberg ,  Vivekananda P. Adiga ,  Rasit O. Topaloglu

    IPC: H01L27/18 ,  H01L39/02 ,  H01L39/24 ,  G06N10/00

    Abstract: A fluxonium qubit includes a superinductor. The superinductor includes a substrate, and a first vertical stack extending in a vertical direction from a surface of the substrate. The first vertical stack includes a first Josephson junction and a second Josephson junction connected in series along the vertical direction. The superinductor includes a second vertical stack extending in a vertical direction from a surface of the substrate. The second vertical stack includes a third Josephson junction. The superinductor includes a superconducting connector connecting the first and second vertical stacks in series such that the first, second, and third Josephson junctions are connected in series. The fluxonium qubit further includes a shunted Josephson junction connected to the superinductor with superconducting wires such that the first, second, and third Josephson junctions of the superinductor that are in series are connected in parallel with the shunted Josephson junction.

    AIRGAP VIAS IN ELECTRICAL INTERCONNECTS
    46.
    发明申请
    AIRGAP VIAS IN ELECTRICAL INTERCONNECTS 审中-公开

    公开(公告)号：US20200126842A1

    公开(公告)日：2020-04-23

    申请号：US16165251

    申请日：2018-10-19

    Applicant: International Business Machines Corporation

    Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

    IPC: H01L21/768 ,  H01L23/522

    Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

    Wire lineend to via overlap optimization
    47.
    发明授权
    Wire lineend to via overlap optimization 有权

    公开(公告)号：US10394992B2

    公开(公告)日：2019-08-27

    申请号：US15805178

    申请日：2017-11-07

    Applicant: International Business Machines Corporation

    Inventor： Rasit O. Topaloglu

    IPC: G06F17/50 ,  G03F1/36

    Abstract: An approach for shifting a cut associated with a lineend of an interconnect in a manufacturing system. The approach selects one or more polygons associated with the lineend and determines whether a first cut is spanning the one or more polygons. The approach responds to the first cut does span, determines a presence of a first via on a first interconnect and determines a first distance of the first via to the first cut. The approach determines whether the first distance is greater than a first threshold and responds to the first distance is greater and determines whether the first distance is greater and determines a second distance of the first cut to a second cut. The approach determines whether the second distance is greater than a second threshold and responds to the second distance is greater and generates a shift associated with the first cut and outputs the shift.

    VERTICAL SUPERCONDUCTING CAPACITORS FOR TRANSMON QUBITS
    48.
    发明申请
    VERTICAL SUPERCONDUCTING CAPACITORS FOR TRANSMON QUBITS 审中-公开

    公开(公告)号：US20190228334A1

    公开(公告)日：2019-07-25

    申请号：US16374505

    申请日：2019-04-03

    Applicant: International Business Machines Corporation

    Inventor： Jared Barney Hertzberg ,  Werner A. Rausch ,  Sami Rosenblatt ,  Rasit O. Topaloglu

    IPC: G06N10/00 ,  H01L39/02 ,  H01L39/24 ,  H01L39/22 ,  H01L27/18

    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

    INTEGRATED CIRCUIT SECURITY
    49.
    发明申请
    INTEGRATED CIRCUIT SECURITY 审中-公开

    公开(公告)号：US20190035746A1

    公开(公告)日：2019-01-31

    申请号：US15662258

    申请日：2017-07-27

    Applicant: International Business Machines Corporation

    Inventor： Kafai Lai ,  Rasit O. Topaloglu

    IPC: H01L23/00 ,  H01L23/544 ,  H01L21/67

    Abstract: A semiconductor product includes a substrate having a self-assembly (SA) pattern. An initial SA pattern is created using a block copolymer (BCP) which has been annealed on the substrate. The initial SA pattern and/or an enlarged SA pattern derived from the initial SA pattern is incorporated into the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product. In other embodiments of the invention a method and system for creating the semiconductor product are described.

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