中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

146 records (took 0.023 seconds)

    Tapered resistive memory with interface dipoles
    41.
    发明授权
    Tapered resistive memory with interface dipoles 有权

    公开(公告)号：US11189786B2

    公开(公告)日：2021-11-30

    申请号：US16587543

    申请日：2019-09-30

    Applicant: International Business Machines Corporation

    Inventor： Reinaldo Vega ,  Takashi Ando ,  Jianshi Tang ,  Praneet Adusumilli

    IPC: H01L45/00

    Abstract: Tapered resistive memory devices with interface dipoles are provided. In one aspect, a ReRAM device includes: a bottom electrode; a core dielectric that is thermally conductive disposed on the bottom electrode; an oxide resistive memory cell disposed along outer sidewalls of the core dielectric, wherein the oxide resistive memory cell has inner edges adjacent to the core dielectric, and outer edges that are tapered; an outer coating disposed adjacent to the outer edges of the oxide resistive memory cell; and a top electrode disposed on the core dielectric, the oxide resistive memory cell, and the outer coating. A method of forming a ReRAM device as well as a method of operating a ReRAM device are also provided.

    Vertical intercalation device for neuromorphic computing
    42.
    发明授权
    Vertical intercalation device for neuromorphic computing 有权

    公开(公告)号：US11164908B2

    公开(公告)日：2021-11-02

    申请号：US16422344

    申请日：2019-05-24

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jianshi Tang ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

    IPC: H01L27/24 ,  G06N3/04 ,  H01L45/00

    Abstract: A semiconductor device with an array of vertically stacked electrochemical random-access memory (ECRAM) devices, includes holes formed in a vertical stack of horizontal electrodes. The horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers. The semiconductor device includes a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and holes. Selector layers fill holes. The selector layers include an inner selector layer and outer selector layers. The channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and a fill layer is deposited over the vertical stack. The fill layer has been reduced down to the top of the inner selector layer.

    Resistive memory with core and shell oxides and interface dipoles
    43.
    发明授权
    Resistive memory with core and shell oxides and interface dipoles 有权

    公开(公告)号：US11145811B2

    公开(公告)日：2021-10-12

    申请号：US16655038

    申请日：2019-10-16

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  Jianshi Tang ,  Praneet Adusumilli ,  Reinaldo Vega

    IPC: G11C11/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: Resistive memory with core and shell oxides and interface dipoles for controlled filament formation is provided. In one aspect, a ReRAM device includes at least one ReRAM cell having a substrate; a bottom electrode disposed on the substrate; spacers formed from a low group electron negativity material disposed on the bottom electrode; a core formed from a high group electron negativity material present between the spacers; and a top electrode over and in contact with the spacers and the core, wherein a combination of the low group electron negativity material for the spacers and the high group electron negativity material for the core generates an interface dipole pointing toward the core. Methods of forming and operating a ReRAM device are also provided.

    Formation of air-gap spacer in transistor
    49.
    发明授权
    Formation of air-gap spacer in transistor 有权
    在晶体管中形成气隙间隔物

    公开(公告)号：US09305835B2

    公开(公告)日：2016-04-05

    申请号：US14190641

    申请日：2014-02-26

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Viraj Sardesai ,  Cung Tran ,  Reinaldo Vega

    IPC: H01L21/76 ,  H01L21/4763 ,  H01L21/70 ,  H01L21/768 ,  H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/7682 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/78 ,  H01L2221/1063

    Abstract: Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces.

    Abstract translation: 本发明的实施例提供了一种在晶体管结构中形成空气间隔物的方法。 该方法包括在半导体衬底的顶部上形成晶体管的栅极结构; 形成邻近所述栅极结构的第一和第二侧壁的第一和第二一次性间隔件; 在第一和第二一次性间隔件旁边形成第一和第二导电柱; 去除所述第一和第二一次性间隔件以在所述第一和第二导电柱和所述栅结构之间产生空的空间; 并通过在空的空间的顶部形成电介质塞来保留空的空间。

Patent Agency Ranking