公开(公告)号：US06225552B1

公开(公告)日：2001-05-01

申请号：US09029611

申请日：1998-03-11

申请人： Kazuo Nishi ,  Makoto Hosokawa ,  Yukihiro Isobe ,  Hideaki Ninomiya

发明人： Kazuo Nishi ,  Makoto Hosokawa ,  Yukihiro Isobe ,  Hideaki Ninomiya

IPC分类号： H01L3100

CPC分类号： H01L31/046 ,  G04C10/02 ,  H01L31/0463 ,  H01L31/0465 ,  Y02E10/50

摘要： The invention relates to a desired shaped plane type solar cell. The solar cell includes a plurality of photoelectric conversion devices formed by dividing the plane, a plurality of conductive paths for connecting each of the photoelectric conversion devices to each other in series, the conductive path being provided adjacent to the plurality of photoelectric conversion devices, and two drawing electrodes exposed on an opposite surface to a light irradiated surface, the electrodes being connected to two photoelectric conversion devices on both ends of the photoelectric conversion device connected in series.

摘要翻译： 本发明涉及一种所需的成形平面型太阳能电池。 太阳能电池包括多个光电转换装置，其通过将平面划分成多个导电路径，用于将每个光电转换装置彼此串联连接，导电路径设置成与多个光电转换装置相邻，以及 两个绘制电极在与光照射表面相反的表面上暴露，电极连接到串联连接的光电转换装置两端的两个光电转换装置。

公开(公告)号：US07211861B2

公开(公告)日：2007-05-01

申请号：US11154743

申请日：2005-06-17

申请人： Satoshi Teramae ,  Shigeru Hasegawa ,  Hideaki Ninomiya ,  Masahiro Tanaka

发明人： Satoshi Teramae ,  Shigeru Hasegawa ,  Hideaki Ninomiya ,  Masahiro Tanaka

IPC分类号： H01L29/06

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/41741

摘要： An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.

摘要翻译： 一种绝缘栅半导体器件，包括沿着半导体衬底的周边形成在循环部分中的隔离结构，以将该部分与内部器件区域隔离，位于隔离结构外部的半导体衬底的外围扩散区域，多个电池单元 在内部器件区域中限定的结构，并由绝缘的沟槽形状的栅极分割成具有覆盖在其上表面的发射极区域的基极区域，集电极区域和与发射极区域和基极区域电连接的发射极电极 ，与单元结构邻接的虚拟基极区域，并且被配置为具有其上表面没有发射极区域连接到发射极电极的基极区域，限定在虚拟基极区域中并与虚拟基极区域绝缘的内部区域，以及连接部分 将内部区域电连接到发射极。

公开(公告)号：US07119379B2

公开(公告)日：2006-10-10

申请号：US10689608

申请日：2003-10-22

申请人： Hideaki Ninomiya ,  Tomoki Inoue

发明人： Hideaki Ninomiya ,  Tomoki Inoue

IPC分类号： H01L29/32 ,  H01L29/94 ,  H01L29/768 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L29/0619 ,  H01L29/0692 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

公开(公告)号：US20060202308A1

公开(公告)日：2006-09-14

申请号：US11434185

申请日：2006-05-16

申请人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

发明人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

IPC分类号： H01L27/082

CPC分类号： H01L29/7397 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7395

摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.

公开(公告)号：US20060127568A1

公开(公告)日：2006-06-15

申请号：US10542846

申请日：2004-01-20

申请人： Kiyoshi Hatanaka ,  Hideaki Ninomiya ,  Haruo Nishino ,  Takeshi Takahashi

发明人： Kiyoshi Hatanaka ,  Hideaki Ninomiya ,  Haruo Nishino ,  Takeshi Takahashi

IPC分类号： B05D5/12

CPC分类号： H05K1/0306 ,  H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0187 ,  H01L2924/00

摘要： A plurality of first green sheets forming first ceramic layers after firing are stacked to form a first pre-fired substrate 4. Next, a plurality of second green sheets forming second ceramic layers after firing are stacked to form a second pre-fired substrate. Next, the first pre-fired substrate 4 is formed with recesses 10. Next, first pre-fired blocks 6 of sizes fitting into the recesses are formed from the second pre-fired substrate. The first pre-fired blocks 6 are fit into the recesses 10 so that the stacking direction A of the first green sheets and the stacking direction A′ of the second green sheets become the same. The first pre-fired substrate 4 in which the first pre-fired blocks 6 are fit is fired.

摘要翻译： 在烧成后形成第一陶瓷层的多个第一生片层叠，形成第一预烧基板4。 接下来，堆叠在焙烧后形成第二陶瓷层的多个第二生片，以形成第二预烧基板。 接下来，第一预烧基板4形成有凹部10。 接下来，由第二预烧基板形成装配到凹部中的尺寸的第一预烧块6。 第一预烧块6装配到凹部10中，使得第一生坯的堆叠方向A和第二生坯的层叠方向A'变得相同。 烧制第一预烧块6的第一预烧基板4。

公开(公告)号：US20050210666A1

公开(公告)日：2005-09-29

申请号：US11072989

申请日：2005-03-07

申请人： Hisao Morooka ,  Hideaki Ninomiya ,  Junichi Shimamura ,  Kazuo Nishi

发明人： Hisao Morooka ,  Hideaki Ninomiya ,  Junichi Shimamura ,  Kazuo Nishi

IPC分类号： C09J5/06 ,  B23P19/00 ,  C09J9/00 ,  C09J133/08 ,  H01L21/00 ,  H01L21/02 ,  H01L31/02 ,  H01L31/0236 ,  H01L31/04 ,  H01L31/18 ,  H05K1/00 ,  H05K3/00 ,  H05K13/00

CPC分类号： H01L31/18 ,  H01L21/67132 ,  H05K1/0393 ,  H05K3/0058 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/5193 ,  Y10T29/53174

摘要： The present invention provides a substrate holding method capable of contributing to improvement in performance of an electronic part. A plastic film is adhered to a holding frame by using an adhesive tape having a proper gas releasing characteristic such that total quantity of gas detected when analysis using gas chromatograph mass spectrometry (dynamic HS-GC-MS) is conducted under test conditions of 180° C. and 10 minutes is 100.5 μg/g or less in n-tetradecane. In the case where the plastic film held by the holding frame is subjected to a process of manufacturing an electronic part (for example, a solar battery), even when a process accompanying generation of heat during the manufacturing process (for example, a film forming process such as plasma CVD) is performed on the plastic film, a release amount of unnecessary gas released from the adhesive tape due to the influence of the heat is suppressed, so that deterioration in the performance of the electronic part caused by the unnecessary gas is suppressed.

摘要翻译： 本发明提供能够有助于提高电子部件的性能的基板保持方法。 通过使用具有适当的气体释放特性的粘合带将塑料膜粘附到保持框架上，使得在使用气相色谱质谱（动态HS-GC-MS）进行分析时检测到的气体总量在180°的测试条件下进行 C.正十四烷中10分钟为100.5马克/克以下。 在由保持框架保持的塑料膜经受制造电子部件（例如，太阳能电池）的处理的情况下，即使在制造过程中伴随发热的处理（例如，成膜 在塑料膜上进行等离子体CVD等工序），能够抑制由于热量的影响而从粘合带释放的不需要的气体的释放量，不利气体导致的电子部件的性能下降 被压制

公开(公告)号：US06774408B2

公开(公告)日：2004-08-10

申请号：US10183454

申请日：2002-06-28

申请人： Hideaki Ninomiya

发明人： Hideaki Ninomiya

IPC分类号： H01L2978

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L21/823487 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7397

摘要： In a trench MOS gate structure of a semiconductor device where trenches (T) are located between an n-type base layer (1) and an n-type source layer (3), a p-type channel layer (12) is formed adjacent to side walls of the trenches, having an even concentration distribution along a depthwise dimension of the trenches. The p-type channel layer enables saturation current to decrease without a raise of ON-resistance of the device, and resultantly a durability against short-circuit can be enhanced. The n-type source layer formed adjacent to the side walls of the trench also further enhances the durability against short-circuit. Providing contacts of the emitter electrode (7) with the n-type source layer at the side walls of the trenches permits a miniaturization of the device and a reduction of the ON-resistance as well.

摘要翻译： 在沟槽（T）位于n型基极层（1）和n型源极层（3）之间的半导体器件的沟槽MOS栅极结构中，形成相邻的p型沟道层（12） 到沟槽的侧壁，沿着沟槽的深度尺寸具有均匀的浓度分布。 p型沟道层能够在不增加器件的导通电阻的情况下降低饱和电流，从而可以提高耐短路性。 与沟槽的侧壁相邻形成的n型源极层还进一步增强了对短路的耐久性。 在沟槽的侧壁处提供发射电极（7）与n型源极层的触点允许器件的小型化以及导通电阻的降低。

公开(公告)号：US06359306B1

公开(公告)日：2002-03-19

申请号：US09606184

申请日：2000-06-29

申请人： Hideaki Ninomiya

发明人： Hideaki Ninomiya

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L21/28202 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7824 ,  H01L29/7825

摘要： In a method of manufacturing a trench-MOS gate structure device, trenches for contact and n-type source layers are alternately formed in a region situated between parallel trench-MOS gates. Thereby, scale down of the device is possible without requiring mask alignment.

摘要翻译： 在制造沟槽MOS栅极结构器件的方法中，用于接触和n型源极层的沟槽交替地形成在平行沟槽MOS栅极之间的区域中。 因此，可以在不需要掩模对准的情况下对器件进行缩小。

公开(公告)号：US5260237A

公开(公告)日：1993-11-09

申请号：US849597

申请日：1992-03-11

申请人： Hideaki Ninomiya ,  Toshinobu Miyakoshi ,  Ryoichi Kondo ,  Takashi Kamiya

发明人： Hideaki Ninomiya ,  Toshinobu Miyakoshi ,  Ryoichi Kondo ,  Takashi Kamiya

IPC分类号： C04B41/86 ,  C03C3/072 ,  C03C8/10 ,  C03C8/14 ,  C03C4/16

CPC分类号： C03C8/10 ,  C03C8/14

摘要： An overcoating inorganic composition is applied to a ceramic substrate for forming an overcoat thereon which has improved flexural strength, matches in thermal expansion with the substrate, and is reliable in that it is free of a crack and causes no variation in the resistance of thick film resistors even under rigorous service conditions. The overcoating inorganic composition contains 70-90% by volume of an inorganic glass component and 10-30% by volume of mullite powder and has a coefficient of thermal expansion in the range of from 50.times.10.sup.-7 to 75.times.10.sup.7 /.degree. C.

摘要翻译： 将外涂层无机组合物施加到陶瓷基材上以形成外涂层，其具有改善的弯曲强度，与基板的热膨胀匹配，并且是可靠的，因为它没有裂纹，并且不会导致厚膜的电阻变化 电阻甚至在严格的使用条件下。 外涂层无机组合物含有70-90体积％的无机玻璃组分和10-30体积％的莫来石粉末，其热膨胀系数在50×10 -7至75×10 7 /℃的范围内。

公开(公告)号：US4098725A

公开(公告)日：1978-07-04

申请号：US634150

申请日：1975-11-21

申请人： Hirotaka Yamamoto ,  Hideaki Ninomiya ,  Makoto Kobayashi

发明人： Hirotaka Yamamoto ,  Hideaki Ninomiya ,  Makoto Kobayashi

IPC分类号： C04B35/18 ,  C04B35/19 ,  C04B35/195 ,  C04B35/478 ,  C04B35/71 ,  H01B1/14 ,  H01B3/00 ,  H01C7/02 ,  H01C7/04 ,  H05B3/12 ,  H01B1/08

CPC分类号： C04B35/478 ,  C04B35/18 ,  C04B35/19 ,  C04B35/195 ,  C04B35/71 ,  H01B1/14 ,  H01B3/004 ,  H01C7/022 ,  H01C7/043 ,  H05B3/12

摘要： Low thermally expansive, electroconductive composite sintered ceramics comprised of a phase of at least one ceramics selected from the group consisting of low thermally expansive ceramics and negatively thermally expansive ceramics, having dispersed thereinto substantially in a continuous state a phase of an electroconductive substance such as a metal.

摘要翻译： 低热膨胀导电复合烧结陶瓷，由选自低热膨胀陶瓷和负热膨胀陶瓷的至少一种陶瓷的相组成，其中分散在基本上连续状态下的导电物质如 金属。