中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

59 records (took 0.024 seconds)

    MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL
    42.
    发明申请
    MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL 审中-公开

    公开(公告)号：US20200066627A1

    公开(公告)日：2020-02-27

    申请号：US16108953

    申请日：2018-08-22

    Applicant: INTEL CORPORATION

    Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

    IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48 ,  H01L23/522 ,  H01L23/58 ,  H01L49/02 ,  H01L23/64

    Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

    METHOD, DEVICE AND SYSTEM TO PROTECT CIRCUITRY DURING A BURN-IN PROCESS
    43.
    发明申请
    METHOD, DEVICE AND SYSTEM TO PROTECT CIRCUITRY DURING A BURN-IN PROCESS 审中-公开

    公开(公告)号：US20200003829A1

    公开(公告)日：2020-01-02

    申请号：US16020425

    申请日：2018-06-27

    Applicant: Intel Corporation

    Inventor： William Lambert ,  Kaladhar Radhakrishnan ,  Michael Hill

    IPC: G01R31/28 ,  G05F1/46

    Abstract: Techniques and mechanisms for mitigating damage to voltage regulator (VR) circuitry of a packaged device. In an embodiment, the VR circuitry comprises a circuit leg between a first node and a second node. During a burn-in process, the VR circuitry provides a regulated output voltage to a load circuit via the first node, wherein the output voltage is based on a supply voltage received via the second node. While the VR circuitry provides the regulated output voltage to the load circuit, a supply current is provided to the load circuit via a path which is independent of any leg which is between the first node and the second node. In another embodiment, an integrated circuit (IC) chip of the packaged device comprises the load circuit, and the leg further comprises an off-chip coil structure which is distinct from the IC chip.

    CONFORMAL POWER DELIVERY STRUCTURE FOR DIRECT CHIP ATTACH ARCHITECTURES
    47.
    发明申请
    CONFORMAL POWER DELIVERY STRUCTURE FOR DIRECT CHIP ATTACH ARCHITECTURES 有权

    公开(公告)号：US20230097714A1

    公开(公告)日：2023-03-30

    申请号：US17485208

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： William J. Lambert ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

    Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

    Microelectronic assemblies having magnetic core inductors
    49.
    发明授权
    Microelectronic assemblies having magnetic core inductors 有权

    公开(公告)号：US11450560B2

    公开(公告)日：2022-09-20

    申请号：US16140398

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

    IPC: H01L21/768

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

Patent Agency Ranking